Integrator Series FPGAs: 1200XL and 3200DX Families
QCLKA
QCLKC
Quad
Clock
Module
Quad
Clock
Module
QCLK1
QCLK3
QCLKB
QCLKD
*QCLK1IN
*QCLK3IN
S0 S1
S1 S0
Quad
Clock
Quad
Clock
QCLK2
QCLK4
Module
Module
*QCLK2IN
*QCLK4IN
S0 S1
S1 S0
*QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
Figure 8 • Quadrant Clock Network
JPROBE Register
Boundary Scan Register
Output
MUX
TDO
Bypass
Register
Control Logic
JTAG
TMS
Instruction
Decode
TAP Controller
TCK
JTAG
Instruction
Register
TDI
Figure 9 • 3200DX IEEE 1149.1 Boundary Scan Circuitry
10
Discontinued – v3.0