Integrator Series FPGAs: 1200XL and 3200DX Families
Table 1 • IEEE 1149.1 BST Signals
Table 2 • BST Instructions
Signal
Name
Function
Test Mode
Code
Description
Serial data input for BST instructions and
data. Data is shifted in on the rising edge
of TCK.
Allows the external circuitry and
board-level interconnections to be tested
by forcing a test pattern at the output pins
and capturing test results at the input
pins.
TDI
Test Data In
EXTEST
000
Serial data output for BST instructions
and test data.
TDO
TMS
TCK
Test Data Out
Test Mode Select
Test Clock
Allows a snapshot of the signals at the
device pins to be captured and examined
during device operation.
SAMPLE/
PRELOAD
Serial data input for BST mode. Data is
shifted in on the rising edge of TCK.
001
011
100
Clock signal to shift the BST data into
the device.
A private instruction allowing the user to
connect Actel’s Micro Probe registers to
the test chain.
JPROBE
JTAG
Allows the user to build
application-specific instructions such as
RAM READ and RAM WRITE.
USER
INSTRUCTION
All 3200DX devices are IEEE 1149.1 (JTAG) compliant.
3200DX devices offer superior diagnostic and testing
capabilities by providing JTAG and probing capabilites.
These functions are controlled through the special JTAG
pins in conjunction with the program fuse.
Refer to the IEEE Standard 1149.1
specification.
HIGH Z
CLAMP
101
110
Refer to the IEEE Standard 1149.1
specification.
Enables the bypass register between the
TDI and TDO pins. The test data passes
through the selected device to adjacent
devices in the test chain.
JTAG fuse programmed:
BYPASS
111
• TCK must be terminated—logical high or low doesn’t
matter (to avoid floating input)
JTAG BST Instructions
• TDI, TMS may float or at logical high (internal pull-up is
present)
JTAG BST testing within the 3200DX devices is controlled
by a Test Access Port (TAP) state machine. The TAP
controller drives the three-bit instruction register, a bypass
register, and the boundary scan data registers within the
device. The TAP controller uses the TMS signal to control
the JTAG testing of the device. The JTAG test mode is
determined by the bitstream entered on the TMS pin. The
table in the next column describes the JTAG instructions
supported by the 3200DX.
• TDO may float or connect to TDI of another device (it’s an
output)
JTAG fuse not programmed:
• TCK, TDI, TDO, TMS are user I/O. If not used, they will be
configured as tristated output.
BST Instructions
Boundary scan testing within the 3200DX devices is
controlled by a Test Access Port (TAP) state machine. The
TAP controller drives the three-bit instruction register, a
bypass register, and the boundary scan data registers within
the device. The TAP controller uses the TMS signal to
control the testing of the device. The BST mode is
determined by the bitstream entered on the TMS pin.
Table 2 describes the test instructions supported by the
3200DX devices.
Design Tool Support ActionProbe
If a device has been successfully programmed and the
security fuse has not been programmed, any internal logic
or I/O module output can be observed in real time using the
ActionProbe circuitry, the PRA and/or PRB pins, and Actel’s
Silicon Explorer diagnostic and debug tool kit.
Reset
The TMS pin is equipped with an internal pull-up resistor.
This allows the TAP controller to remain in or return to the
Test-Logic-Reset state when there is no input or when a
logical 1 is on the TMS pin. To reset the controller, TMS
must be HIGH for at least five TCK cycles.
When a device is operating in BST mode, four I/O pins are
used for the TDI, TDO, TMS, and TCLK signals. An active
reset (nTRST) pin is not supported; however, the 3200DX
contains power-on circuitry which automatically resets the
BST circuitry upon power-up. The following table
summarizes the functions of the BST signals.
Discontinued – v3.0
11
ACTEL [ Actel Corporation ]
