A C T
™
2 F a m il y F PG A s
A CT 2 Ti m i n g M od el *
Input Delays
Internal Delays
Combinatorial
I/O Module
Logic Module
t
INYL
= 2.6 ns t
= 4.8 ns
†
IRD2
Predicted
Routing
Delays
Output Delays
I/O Module
t
DLH
= 8.0 ns
D
Q
t
PD
= 3.8 ns
t
RD1
= 1.4 ns
t
RD2
= 1.7 ns
t
RD4
= 3.1 ns
t
RD8
= 4.7 ns
G
t
INH
= 2.0 ns
t
INSU
= 4.0 ns
t
INGL
= 4.7 ns
Sequential
Logic Module
Combin-
atorial
Logic
included
in t
SUD
ARRAY
CLOCKS
t
SUD
= 0.4 ns
t
HD
= 0.0 ns
I/O Module
t
DLH
= 8.0 ns
D
Q
t
RD1
= 1.4 ns
D
Q
t
ENHZ
= 7.1 ns
G
t
OUTH
= 0.0 ns
t
OUTSU
= 0.4 ns
t
GLH
= 9.0 ns
t
CO
= 3.8 ns
t
CKH
= 11.8 ns
F
MAX
= 100 MHz
FO = 256
*Values shown for A1240A-2 at worst-case commercial conditions.
† Input Module Predicted Routing Delay
v4.0
7
ACTEL [ Actel Corporation ]
