A C T 1 T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )
Input Module Propagation Delays
Parameter Description
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t
t
Pad to Y High
Pad to Y Low
3.1
3.1
3.5
3.5
4.0
4.0
4.7
4.7
6.8
6.8
ns
ns
INYH
INYL
1
Input Module Predicted Routing Delays
t
t
t
t
t
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
0.9
1.4
2.1
3.1
6.6
1.1
1.7
2.5
3.6
7.7
1.2
1.9
2.8
4.1
8.7
1.4
2.2
2.0
3.2
ns
ns
ns
ns
ns
IRD1
IRD2
IRD3
IRD4
IRD8
3.3
4.8
4.8
7.0
10.2
14.8
Global Clock Network
t
t
t
t
t
t
f
Input Low to High
FO = 16
FO = 128
4.9
5.6
5.6
6.4
6.4
7.3
7.5
8.6
6.7
7.9
CKH
CKL
PWH
PWL
CKSW
P
ns
ns
ns
ns
ns
ns
Input High to Low
FO = 16
FO = 128
6.4
7.0
7.4
8.1
8.4
9.2
9.9
10.8
8.8
10.0
Minimum Pulse Width
High
FO = 16
FO = 128 6.8
6.5
7.5
8.0
8.5
9.0
10.0
10.5
8.9
9.8
Minimum Pulse Width
Low
FO = 16 6.5
FO = 128 6.8
7.5
8.0
8.5
9.0
10.0
10.5
8.9
9.8
Maximum Skew
FO = 16
FO = 128
1.2
1.8
1.3
2.1
1.5
2.4
1.8
2.8
1.5
2.4
Minimum Period
Maximum Frequency
FO = 16
FO = 128 14.2
13.2
15.4
16.7
17.6
18.9
20.9
22.3
18.2
20
FO = 16
FO = 128
75
70
65
60
57
53
48
45
55
MAX
50 MHz
Note:
1. These parameters should be used for estimating device performance. Optimization techniques may further reduce delays by 0 to 4 ns.
Routing delays are for typical designs across worst-case operating conditions. Post-route timing analysis or simulation is required to
determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior
to shipment.
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