E q u iv a le n t C a p a c it a n c e
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
CEQO = Equivalent capacitance of output buffers in pF
Power (uW) = CEQ * VCC2 * F
(1)
CEQCR = Equivalent capacitance of routed array clock in
pF
Where:
CEQ is the equivalent capacitance expressed in pF.
CL
fm
fn
= Output lead capacitance in pF
V is the power supply in volts.
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
CC
F is the switching frequency in MHz.
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
fp
fq1
= Average first routed array clock rate in MHz (All
families)
range of frequencies at a fixed value of V . Equivalent
CC
capacitance is frequency independent so that the results may
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
F ix e d C a p a c it a n c e Va lu e s fo r Ac t e l F P G As
(p F )
r1
C
Va lu e s fo r Ac t e l F P G As
E Q
Device Type
A1010B
routed_Clk1
41.4
68.6
40
A10V10B
A10V20B
A1010B
A1020B
A1020B
Modules (CEQM
Input Buffers (CEQI
Output Buffers (CEQO
Routed Array Clock Buffer
Loads (CEQCR
)
3.2
10.9
11.6
3.7
22.1
31.2
A10V10B
A10V20B
)
65
)
De t e r m in in g Av e r a g e S w it c h in g F r e q u e n c y
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
)
4.1
4.6
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
Logic Modules (m)
90% of modules
#inputs/4
Power = V 2 * [(m * CEQM * fm)modules
+
CC
Inputs switching (n)
(n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs
0.5 * (q1 * CEQCR * fq1)routed_Clk1
(r1 * fq1)routed_Clk1
+
Outputs switching (p)
First routed array clock loads (q1)
Load capacitance (CL)
#outputs/4
40% of modules
35 pF
+
]
(2)
Where:
Average logic module switching rate (fm) F/10
m
n
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
Average input switching rate (fn)
Average output switching rate (fp)
F/5
F/10
p
Average first routed array clock rate F
(fq1)
q1
= Number of clock loads on the first routed array
clock (All families)
r1
= Fixed capacitance due to first routed array
clock (All families)
1 -2 9 0
ACTEL [ Actel Corporation ]
