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A10V10B-1CQ84M 参数 Datasheet PDF下载

A10V10B-1CQ84M图片预览
型号: A10V10B-1CQ84M
PDF下载: 下载PDF文件 查看货源
内容描述: ACT 1系列FPGA [ACT 1 Series FPGAs]
分类和应用:
文件页数/大小: 24 页 / 163 K
品牌: ACTEL [ Actel Corporation ]
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A C T  
1 S e r i e s F P G A s  
A C T 1 T i m i n g C h a r a c t e r i s t i c s  
1
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s , V  
Logic Module Propagation Delays  
Parameter Description  
= 4 . 7 5 V, T = 7 0 °C )  
J
C C  
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed  
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units  
t
t
t
t
t
Single Module  
2.9  
6.8  
2.9  
2.9  
2.9  
3.4  
7.8  
3.4  
3.4  
3.4  
3.8  
8.8  
3.8  
3.8  
3.8  
4.5  
10.4  
4.5  
6.5  
15.1  
6.5  
ns  
ns  
ns  
ns  
ns  
PD1  
PD2  
CO  
Dual Module Macros  
Sequential Clk to Q  
Latch G to Q  
4.5  
6.5  
GO  
RS  
Flip-Flop (Latch) Reset to Q  
4.5  
6.5  
2
Predicted Routing Delays  
t
t
t
t
t
FO=1 Routing Delay  
FO=2 Routing Delay  
FO=3 Routing Delay  
FO=4 Routing Delay  
FO=8 Routing Delay  
0.9  
1.4  
2.1  
3.1  
6.6  
1.1  
1.7  
2.5  
3.6  
7.7  
1.2  
1.9  
2.8  
4.1  
8.7  
1.4  
2.2  
2.0  
3.2  
ns  
ns  
ns  
ns  
ns  
RD1  
RD2  
RD3  
RD4  
RD8  
3.3  
4.8  
4.8  
7.0  
10.2  
14.8  
3
Sequential Timing Characteristics  
t
t
t
t
t
Flip-Flop (Latch) Data Input Setup  
Flip-Flop (Latch) Data Input Hold  
Flip-Flop (Latch) Enable Setup  
Flip-Flop (Latch) Enable Hold  
5.5  
0.0  
5.5  
0.0  
6.4  
0.0  
6.4  
0.0  
7.2  
0.0  
7.2  
0.0  
8.5  
0.0  
8.5  
0.0  
10.0  
0.0  
ns  
ns  
ns  
ns  
SUD  
4
HD  
10.0  
0.0  
SUENA  
HENA  
Flip-Flop (Latch) Clock Active Pulse  
Width  
WCLKA  
6.8  
8.0  
9.0  
10.5  
9.8  
ns  
t
Flip-Flop (Latch)  
WASYN  
Asynchronous Pulse Width  
6.8  
8.0  
9.0  
10.5  
22.3  
9.8  
ns  
ns  
t
f
Flip-Flop Clock Input Period  
14.2  
16.7  
18.9  
20.0  
A
Flip-Flop (Latch) Clock  
Frequency (FO = 128)  
MAX  
70  
60  
53  
45  
50  
MHz  
Notes:  
1.  
V
= 3.0 V for 3.3V specifications.  
CC  
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device  
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based  
on actual routing delay measurements performed on the device prior to shipment.  
3. Setup times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility.  
4. The Hold Time for the DFME1A macro may be greater than 0 ns. Use the Designer 3.0 or later Timer to check the Hold Time for this macro.  
1 -2 9 7  
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