™
A C T
1 S e r i e s F P G A s
A C T 1 T i m i n g C h a r a c t e r i s t i c s (c o n t in u e d )
(Wo r s t -C a s e C o m m e r c ia l C o n d it io n s )
Output Module Timing
Parameter Description
TTL Output Module Timing
‘–3’ Speed ‘–2’ Speed ‘–1’ Speed ‘Std’ Speed 3.3 V Speed
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
1
t
t
t
t
t
t
Data to Pad High
6.7
7.5
7.6
8.6
8.7
9.8
10.3
11.5
10.2
12.2
15.4
13.9
0.09
0.12
15.0
16.7
14.8
17.7
22.4
20.2
ns
ns
ns
ns
ns
ns
DLH
Data to Pad Low
DHL
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
Delta Low to High
6.6
7.5
8.6
ENZH
ENZL
ENHZ
ENLZ
7.9
9.1
10.4
13.1
11.8
0.08
0.10
10.0
9.0
11.6
10.4
0.07
0.09
d
d
0.06
0.08
0.13 ns/pF
0.17 ns/pF
TLH
THL
Delta High to Low
1
CMOS Output Module Timing
t
t
t
t
t
t
Data to Pad High
7.9
6.4
9.2
7.2
10.4
8.2
12.2
9.8
17.7
14.2
13.4
18.5
22.4
20.2
ns
ns
ns
ns
ns
ns
DLH
Data to Pad Low
DHL
Enable Pad Z to High
Enable Pad Z to Low
Enable Pad High to Z
Enable Pad Low to Z
Delta Low to High
Delta High to Low
6.0
6.9
7.9
9.2
ENZH
ENZL
ENHZ
ENLZ
8.3
9.4
10.7
13.1
11.8
0.13
0.08
12.7
15.4
13.9
0.15
0.09
10.0
9.0
11.6
10.4
0.11
0.07
d
d
0.10
0.06
0.22 ns/pF
0.13 ns/pF
TLH
THL
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the “Simultaneous Switching Output Limits for Actel FPGAs” application note on page 4-125.
1 -2 9 9
ACTEL [ Actel Corporation ]
