HiRel FPGAs
Dual-Port SRAM Timing Waveforms
3200DX SRAM Write Operation
tRCKHL
tRCKHL
WCLK
tADSU
tADH
WD[7:0]
WRAD[5:0]
Valid
tWENSU
tWENH
WEN
tBENSU
Valid
tBENH
BLKEN
Note: Identical timing for falling-edge clock.
3200DX SRAM Synchronous Read Operation
tCKHL
tRCKHL
RCLK
tRENSU
tRENH
REN
tADSU
Valid
tADH
RDAD[5:0]
tRCO
tDOH
Old Data
New Data
RD[7:0]
Note: Identical timing for falling-edge clock.
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