™
A C T
1 S e r i e s F P G A s
F u n c t i o n a l T i m i n g T e s t s
logic modules are distributed along two sides of the device, as
inverting or non-inverting buffers. The modules are
connected through programmed antifuses with typical
capacitive loading.
AC timing for logic module internal delays is determined
after place and route. The DirectTime Analyzer utility
displays actual timing parameters for circuit delays. ACT 1
devices are AC tested to a “binning” circuit specification.
Propagation delay [tPD = (tPLH + tPHL)/2] is tested to the
following AC test specifications.
The circuit consists of one input buffer + n logic modules +
one output buffer (n = 16 for A1010B; n = 28 for A1020B). The
O u t p u t B u f f e r P e r f o r m a n c e D e r a t i n g ( 5 V )
Sink
Source
12
–4
10
8
–6
–8
6
4
–10
–12
0.2
0.3
0.4
0.5
0.6
4.0
3.6
3.2
2.8
2.4
2.0
V
(Volts)
V
(Volts)
OL
OH
Military, worst-case values at 125°C, 4.5 V.
Commercial, worst-case values at 70°C, 4.75 V.
Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices.
O u t p u t B u f f e r P e r f o r m a n c e D e r a t i n g ( 3 . 3 V )
Sink
Source
12
10
–4
–6
8
–8
6
4
–10
–12
0
0.0
0.1
0.2
0.3
0.4
0.5
1.0
1.5
2.0
2.5
V
(Volts)
V
(Volts)
OL
OH
Commercial, worst-case values at 70°C, 4.75 V.
Note: The above curves are based on characterizations of sample devices and are not completely tested on all devices.
1 -2 9 1
ACTEL [ Actel Corporation ]
