MIL-PRF-38535K
APPENDIX H
c. Time dependent dielectric breakdown (TDDB) (MOS). The TCV should contain structures for characterizing TDDB of
gate oxides. The structures should have gate oxide area and perimeter dominated structures. Separate perimeter
structures should be used for the gate ending on a source or drain boundary and where the gate terminates over the
transistor-to-transistor isolation oxide. The electric field and temperature acceleration factors for TDDB should be
determined and a MTTF and failure distribution determined for the worst case voltage conditions and thinnest gate
oxide allowed in the technology. From the MTTF, a failure rate for TDDB in the technology should be calculated.
d. TCV fast test structure requirements. The structures to be used for the fast test reliability monitoring of hot electron
aging should be included in the TCV program so that correlations of the fast-test measurements with the accelerated
aging results may be made.
NOTE: It is strongly recommended that fast test intrinsic reliability structures for electromigration and TDDB be
included in the TCV program so that correlations can be made with longer term aging experiments. It is likely that
these structures shall be required for wafer acceptance in the future.
e. Ohmic contact degradation. The TCV should have a structure for assessing the degradation of ohmic contacts with
time at temperature, especially for gallium arsenide (GaAs).
f.
Sidegating/backgating. A structure should be included for evaluating sidegating/backgating of field effect transistor’s
(FET's) in GaAs technology.
g. Sinking gate. A FET structure should be included for evaluating the sinking gate degradation mechanism and other
channel degradation mechanisms of GaAs FET's.
h. Threshold voltage instability, including Negative Bias Temperature Instability (NBTI) for 130 nm and smaller CMOS
technologies. The NBTI test structure evaluates the effect due to interface traps (oxide energy states) in the gate
oxide that form under DC inversion stress. Holes in the PMOS devices are known to interact with these traps more
easily than electrons, and so this is a PMOS dominated mechanism. These trapped holes cause the threshold
voltage (VTH) of the affected transistor to shift lower (more negative) with increasing temperature, degrading device
performance.
H.3.2.2.3 Assembly and packaging. The manufacturer should list the assembly and packaging processes (die-attachment,
wire/ribbon bonding, seal molding and part marking) that is expected to be listed on the QML and used in QML microcircuit
assembly (see H.3.2.1.5).
H.3.2.2.3.1 Assembly process technology. New assembly process technologies shall be characterized to determine the
mechanical and thermal performance. The technology's susceptibility to intrinsic reliability failure mechanisms shall be
characterized to determine potential failure modes. The characterizations may include performance of thermal stresses at
multiple temperature levels to develop derating curves. Tables H-IA and H-IB identify the assembly process qualification testing
which shall be addressed for the technology being used.
H.3.2.2.3.2 Packaging technology. The manufacturer shall address package design/construction quality and reliability.
The manufacturer is responsible to maintain documented validation of all characterization methods used, including all
supporting data (see H.3.2.1.1.3). Tables H-IIA and H-IIB identify the key package characteristics for which testing shall be
addressed on each QML package technology.
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ACTEL [ Actel Corporation ]
