MIL-PRF-38535K
APPENDIX H
(6) GaAs FET parameters: FET test structures should be included, suitable for RF probing, which can be used for
measurement of both DC and RF FET parameters. The following parameters should be measured:
(a)
Idss - saturated drain current at zero gate bias.
(b) gm - transconductance at saturation and at 50 percent Idss
(c) Pinch off voltage.
.
(d) Gate-drain leakage and breakdown voltage.
(e) Gate-source breakdown voltage.
(f) Source and drain resistance.
(g) S-parameters of FET over frequency range of technology.
e. Fast-test reliability structures. Fast-test reliability structures are structures meant to evaluate, within a few seconds of
testing, a particular known reliability failure mechanism to insure that the processing which an individual wafer
received is consistent with the reliability goals of the technology. The fast-test structures are in general new and, with
the exception of hot carrier aging structures, are not sufficiently mature. Development work on them is intense
however, and it is intended that these structures when mature, shall become a mandatory part of the PM. For this
reason it has been decided to include information regarding fast-test reliability structures in the following paragraphs.
Documentation should be available which shows the correlation between fast-tests and the results of the more
traditional accelerated aging tests performed on the TCV.
(1) Hot carrier aging: A fast-test structure should be included to evaluate the susceptibility of MOS transistors to hot
electron aging. This structure may be one of the PM test transistors.
(2) Electromigration: Worst-case design rule fast-test structures should be included to evaluate the susceptibility of
each metal level and the associated contacts to electromigration.
(3) Time dependent dielectric breakdown (TDDB): Fast-test structures should be included that can evaluate the
long-term reliability of gate oxides.
(4) Contact resistance: Fast-test structures should be included that can evaluate the long-term reliability of contacts.
(5) Gate diffusion: Fast-test structures should be included that can evaluate the long-term reliability of the gate
contact.
(6) Threshold voltage instability, including Negative Bias Temperature Instability (NBTI) for 130 nm and smaller
CMOS technologies.
H.3.2.1.4 Wafer acceptance plan. The TRB should develop and demonstrate a wafer acceptance plan based on electrical
and radiation (if applicable) measurement of PMs. This plan should utilize the PM and should include visual criteria, if
applicable.
For wafer lot acceptance tests shall be performed in accordance with TM 5007 of MIL-STD-883 or an alternative which
meets the minimum requirements of TM 5007 on each wafer lot producing class V or class Y (class level S) devices. The use
of TM 5013 of MIL-STD-883 is encouraged for GaAs technology devices. In addition, this plan should address the concerns
detailed in TM 2018 of MIL-STD-883 (e.g., metallization, step coverage). The use of TM 2018 is encouraged, however
alternate procedures utilizing PMs and in-line monitors are accepted if approved during validation. PM data should be recorded
and made available for review.
This plan can be either a wafer by wafer acceptance plan or a wafer lot acceptance plan, but shall address the following
concerns:
a. Small lots.
b. Large lots.
c. Specialty lots.
162
ACTEL [ Actel Corporation ]
