MIL-PRF-38535K
APPENDIX H
H.3.2.1.6 SPC and in-process monitoring program. A process monitoring system should be used by a manufacturer to
control key processing steps to insure product yield and reliability. The monitoring system can utilize various test chips,
methods and measurement techniques. The critical operations to be monitored shall be determined by the manufacturer based
on their experience and knowledge of their processes. The resulting data should be analyzed by appropriate SPC methods to
determine control effectiveness. The following should be addressed, as a minimum, by the manufacturer:
a. Incoming assembly process materials.
b. Incoming package acceptance.
c. Equipment used for assembly.
d. Wafer acceptance criteria.
e. Die attach.
f. Chip to package interconnect (wire/ribbon bond, tab, flip chip).
g. Package seal.
h. Marking.
i. Rework.
j. Lead trim, form, and final finish.
k. Atmosphere and cleanliness control.
l. Chip encapsulation/molding.
m. Encapsulant purity.
n. Internal water vapor.
o. Flip chip die pull off test shall be performed (before underfill dispense) in accordance with TM 2031
and bump shear test shall be performed for wafer bump technology qualification.
p. Balls/Columns attach.
H.3.2.1.7 Test capability. The manufacturer shall document test capability to their QM plan, which includes devices
screening, qualification and technology conformance test conditions in accordance with the applicable Standard Microcircuits
Drawing (SMD), MIL-PRF-38535, and MIL-STD-883, as applicable to the product.
H.3.2.1.8 Certification approval. Upon successful demonstration by the manufacturer of meeting the certification
requirements, the QA will issue a certification of approval. This certification will include QA approved alternatives and test
optimizations as presented by the manufacturer and listed in the QM plan. Documentation and data presented by the
manufacturer during the certification process does not need to be provided as a part of the reliability assessment and
qualification stages.
H.3.2.2 Physics-of- failure/TCV reliability assessment.
H.3.2.2.1 Reliability assessment plan. For class level S product, the manufacturer shall provide to the QA a reliability
assessment plan for the technology. The plan shall account for all significant failure mechanisms as listed in the following
sections.
H.3.2.2.2 TCV program . A TCV program should be implemented by the manufacturer for the technology or process being
considered for certification. The program should contain, as a minimum, those test structures needed to characterize a
technology's susceptibility to intrinsic reliability failure mechanisms such as electromigration, time dependent dielectric
breakdown (TDDB), gate sinking, ohmic contact degradation, sidegating/backgating, hot carrier aging and threshold voltage
instability, including Negative Bias Temperature Instability (NBTI). If other wear-out mechanisms are discovered as integrated
circuit technology continues to mature, test structures for the new wear out mechanisms should be added to the TCV program.
The TCV program shall be used for the following purposes: Certification of the technology; reliability monitoring; radiation
hardness assurance and monitoring, when applicable; change control; and the characterization of fast-test intrinsic reliability
structures.
NOTE: The test structures necessary to monitor intrinsic reliability failure mechanisms do not have to be a single die or
location, but can appear on the PM, the SEC, or the device itself. The TCV program (see G.3.3.f) should, however, indicate
where the structures are located and how they are tested and analyzed.
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ACTEL [ Actel Corporation ]
