MIL-PRF-38535K
APPENDIX H
o. Ion implant.
p. Wafer backside preparation.
q. Wafer probe acceptance criteria.
r. Rework policy.
s. Oxide process.
t. Gate formation.
u. Air bridge process.
v. Via hole process.
w. Clean room procedures.
x. Change control system/notification.
y. Lot travelers (ref. A.3.4.6, A.3.4.6.1)
z. Equipment calibration and preventive maintenance.
aa. Wafer traceability.
ab. Wafer acceptance plan.
ac. Wafer bump characteristics (height, width etc.,)
H.3.2.1.3.1 SPC and in-process monitor checklist (Class level S) . The following items shall be used as minimum
requirements, as applicable for the technology, for the manufacturer and QA in evaluating the new technology for class level S
product:
a. Define SPC monitor points.
b. Define control limits and absolute limits.
c. Review of data by the manufacturer and QA.
d. Out of control (OOC) action plans.
e. Radiation performance, if applicable.
f. Process capability (CPK) trigger level.
g. Sample data for any prime lot reviewed by the manufacturer and QA (Prime lot is defined as a lot meeting all
process monitor requirements with no MRB or out of control actions implemented).
h. SPC controls in place audited by the QA.
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ACTEL [ Actel Corporation ]
