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5962-0422102QZA 参数 Datasheet PDF下载

5962-0422102QZA图片预览
型号: 5962-0422102QZA
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 32256-Cell, CMOS, CBGA624,]
分类和应用: 可编程逻辑
文件页数/大小: 52 页 / 373 K
品牌: ACTEL [ Actel Corporation ]
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TABLE IIB. Delta limits at +25C - Continued.  
4/ The binning circuit has two different paths to measure the delay due to antifuse contribution and transistor  
contribution. Below shows a simplified schematic of the two binning circuit paths used to measure and characterize  
speed grades by comparing to timing models.  
The “Bin Path 1 (BIN_FAST)” path is composed of inverter chains to measure the delay due to transistors.  
The “Bin Path 2 (BIN_SLOW)” path is mainly composed of metal tracks connected to ground via un-programmed  
antifuses to emulate capacitive loading due to antifuses. In addition to the antifuse capacitive loading, the “Bin Path 2”  
also has in series to the path, a fixed amount of antifuses that get programmed to emulate delays of programmed  
antifuses.  
5/ Binning circuit measurement is done by applying stimulus signals through the TDI pin. The stimulus circuit will apply  
the necessary signals to toggle one path and output the signal to TDO pin. A formula is extracted by correlating the  
measured bin speeds of the two binning circuit paths and the characterization data. For each device, during the  
speed grading in the screening process, the BIN_FAST and BIN_SLOW measurement are used by the formula to  
determine the speed grade of each part.  
4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded  
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical  
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,  
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7,  
and 9.  
4.6 Programming procedures. Programming support is provided through manufacturer’s Silicon Sculptor 2 and 3 (see 6.7  
herein), a single-sited programmer controlled from a PC with manufacturer’s Silicon Sculptor programming software. During  
programming, each antifuse is programmed and verified by the programming algorithm to ensure correct programming. At the  
end of the programming, there are integrity tests to ensure that programming is completed properly. The programming  
procedure is specified by the manufacturer and available at manufacturer’s website. The programming procedures shall be  
maintained by the manufacturer and shall be made available to the preparing or acquiring activity upon request.  
5. PACKAGING  
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes  
Q and V or MIL-PRF-38535, appendix A for device class M.  
6. NOTES  
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications  
(original equipment), design applications, and logistics purposes.  
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor  
prepared specification or drawing.  
6.1.2 Substitutability. Device class Q devices will replace device class M devices.  
SIZE  
STANDARD  
5962-04221  
A
MICROCIRCUIT DRAWING  
DEFENSE SUPPLY CENTER COLUMBUS  
COLUMBUS, OHIO 43218-3990  
REVISION LEVEL  
SHEET  
C
49  
DSCC FORM 2234  
APR 97  
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