Core1553BBC MIL-STD-1553B Bus Controller
CLK
CPUCSN
CPUWRN
CPUADDR
CPUMEM
CPUDIN
ADDR
Data
Write
Tpd
Tpd
CPUWAITN
Figure 13 • CPU Interface Memory Write Cycle
CPUWAITn will be driven low for a minimum of three (3)
clock cycles for write cycles, four (4) for read cycles, and
the number of clock cycles the memory backend delays
the assertion of MEMGNTn and asserts MEMWAITn.
CPUWAITn is driven low by CPURDn/CPUWRn becoming
active and returns high on the falling clock edge after
data is valid.
The CPU interface signals are internally synchronized to
the Core1553BBC master clock. If these inputs are
asynchronous, then CPUCSn, CPUADDR, and CPUDATA
should be valid/invalid before CPUWRn, and remain valid
after CPUWRn. CPUWRn must be active for at least one
clock cycle.
CLK
Tiack
INTOUT
CPURDN
Figure 14 • Interrupt Timing
Memory Timing
CLK
MEMREQn
Tsu
MEMGNTn
MEMCEN
MEMDEN
MEMCSn
MEMADDR
Tsu
MEMDIN
MEMRDn
Tsu
Tsu
MEMWAITn
Figure 15 • Asynchronous Memory Read Cycle
v4.0
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ACTEL [ Actel Corporation ]
