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1553BBC-SR 参数 Datasheet PDF下载

1553BBC-SR图片预览
型号: 1553BBC-SR
PDF下载: 下载PDF文件 查看货源
内容描述: Core1553BBC MIL- STD- 1553B总线控制器 [Core1553BBC MIL-STD-1553B Bus Controller]
分类和应用: 总线控制器
文件页数/大小: 30 页 / 214 K
品牌: ACTEL [ Actel Corporation ]
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Core1553BBC MIL-STD-1553B Bus Controller  
Bus Controller Operation  
After power-up, the bus controller waits while the CPU  
sets up the bus controller memory and registers. The  
memory contains an instruction list, message blocks, and  
data blocks. Once the instruction list, message blocks,  
and data blocks are setup, the CPU starts the bus  
controller. The bus controller works its way through all  
the message blocks until it reaches the end of the  
instruction list (Figure 6).  
The instruction list contains a list of pointers to message  
blocks. The message block contains the command words  
transmitted on the 1553B bus and status words received  
from the 1553B bus. It also contains a pointer to a data  
block. The data block contains the data transmitted on  
the 1553B bus, or the data received from the 1553B bus.  
Instruction  
List  
Message  
Block  
Data  
INSTRUCTION  
PARAMETER  
INSTRUCTION  
PARAMETER  
INSTRUCTION  
PARAMETER  
Block  
MSGCMD  
CW (RTRT RX)  
CW (RTRT TX)  
DATAPTR  
32  
Data Words  
SW (RTRT TX)  
SW (RTRT RX)  
TSW  
Figure 6 BC Memory Usage  
Table 13 Instruction Word  
Instruction List  
15:13  
12:8  
7:4  
3:0  
The instruction list contains pairs of words: an instruction  
and a parameter. Core1553BBC supports a broad set of  
instructions allowing branching and sub-routine calls  
with condition code support. This allows complex  
instruction lists to be supported. The instruction contains  
a 4-bit OPCODE and a 5-bit condition code field (Table 13  
and Table 14).  
Reserved  
CONDCODE  
Reserved  
OPCODE  
All of the OPCODES support the condition code field. If  
the condition is TRUE, then the OPCODE is carried out;  
otherwise, the BC continues to the next instruction. For  
RT-to-RT messages, the condition code will be true if the  
bit is set in either status word or not set in either status  
word (Table 15 on page 14).  
Table 14 Supported Instructions  
OPCODE Function Condition Code Parameter  
Description  
0000  
0001  
0010  
0011  
NOP  
DOMSG  
JUMP  
N/A  
Yes  
Yes  
Yes  
N/A  
No operation, jumps to next message  
Process the message block  
Message Block Address  
New Instruction Address Jumps to the new message list address  
INTR  
User interrupt value  
(Lower eight bits)  
Force a BC interrupt  
0100  
0101  
HALT  
Yes  
Yes  
User interrupt value  
(Lower eight bits)  
Stop the BC  
DELAY  
Timer value  
(Lower eight bits)  
Loads the timer with the parameter and waits until the timer  
reaches zero  
v4.0  
13