Core1553BBC MIL-STD-1553B Bus Controller
Table 12 • Interrupt Register
Bits
15
Name
INTPENDING
INTVECT
Type Function
RW
RW
When set, the BC has an interrupt pending. This bit is set if any of the INTVECT bits are set.
14:8
Interrupt Reason
The CPU writing a '1' to the bit clears the bit.
14 BC has completed the message list, HALT instruction executed
13 INTREQ instruction executed
12 Memory access failure. This bit also directly drives the MEMFAIL output.
11 Asynchronous message is completed, RETAS instruction is executed.
10 Transmitter shutdown is set when the core detects that it has been transmitting continuously
on the bus for greater than 700µs. When set, the BC disables its transmitter.
9
8
Stack pointer overflow or underflow is set if the BC attempts to push more than 256 return
addresses onto the stack or pop of a non-existent address from the stack. The BC stops
operation when this occurs.
Corrupt instruction list or data table.
Illegal command written to the control register, e.g. start instruction while an asynchronous
message is active. The BC stops operation when this occurs.
7:0
USERVECT
R
Provides the user-supplied interrupt reason as set by the instruction parameter
12
v4.0
ACTEL [ Actel Corporation ]
