Core1553BBC MIL-STD-1553B Bus Controller
Product Summary
Intended Use
•
•
1553B Bus Controller (BC)
DMA Backend Interface to External Memory
– Synthesis Scripts
Actel-Developed Testbenches, VHDL and Verilog
•
Synthesis and Simulation Support
•
•
Synthesis: Synplicity
®
, Synopsys
®
(Design Compiler
®
/
FPGA Compiler
TM
/FPGA Express
TM
), Exemplar
TM
Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
Key Features
•
•
Supports MIL-STD-1553B
Interfaces to External RAM
– Supports up to 128kbytes of Memory
– Synchronous
or
Asynchronous
Backend
Interface
– Backend Interface Identical to Core1553BRT
Selectable Clock Rate of 12, 16, 20, or 24 MHz
Provides Direct CPU Access to Memory
Interfaces to Standard 1553B Transceivers
Fully Automated Message Scheduling
– Frame Support
– Conditional Branching and Sub-routines
– Variable Inter-message Gaps and RT Response
Times
– Real Time Clock for Message Scheduling
– Asynchronous Message Support
Verification and Compliance
•
•
•
Actel-Developed Simulation Testbench
Core Implemented on the 1553B BC Development
System
Third-Party 1553B Compliance Testing of the
1553B Encoder and Decoder Blocks Implemented
in an A54SXA32-STD Device
•
•
•
•
Development System (Optional)
•
•
•
Complete 1553B BC Implementation in an SX-A
Device
Includes a PCI Interface for Host CPU Connection
Includes Transceivers
Components
and
Bus
Termination
Supported Families
•
•
•
•
•
•
•
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX
SX-A
RTSX-S
Contents
Core Deliverables
•
Netlist Version
Compiled RTL Simulation Model, Compliant
with the Actel Libero™ Integrated Design
Environment (IDE)
– Compatible with the Actel Designer Place-and-
Route Tool
RTL Version
– VHDL or Verilog Core Source Code
–
•
December 2005
© 2005 Actel Corporation
v 4 .0
1
ACTEL [ Actel Corporation ]
