AL103 Revision 1.0
3.12 Media Independent Interface (MII)
The MAC of each port of the AL103 is connected to the PHY through the standard MII interface.
For receiving frames, the received data (RXD[3:0]) is sampled at the rising edge of the receive
clock (RX_CLK). Assertion of the receive data valid (RX_DV) signal will cause the MAC to look
for start of SFD. For transmission, the transmit data enable (TX_EN) signal is asserted when the
first preamble nibble is sent on the transmit data (TXD[3:0]) lines. The transmit data is clocked out
by the rising edge of the transmit clock (TX_CLK).
Prior to any transaction, the AL103 will output 32-bits of “1” as a preamble signal and then after
the preamble, a “01” signal is used to indicate the start of the frame.
3.13 PHYManagement
The AL103 supports transceiver management through the serial MDIO and MDC signal lines. The
device provides two modes of management, master and slave mode. In the master mode of
operation, the AL103 controls the operation modes of the link but in the slave mode the PHY
controls the operating mode.
3.13.1 PHY Management MDIO
For a write operation, the device will send a “01” to signal a write operation. Following the “01”
write signal their will be the 5-bit ID address of the PHY device and the 5-bit register address. A
“10” turn around signal is then used to avoid contention during a read transaction. After the turn
around, the 16-bit of data will be written into the register and then after the completion of the write
transaction, the line will be put in a high impedance state.
For a read operation, the AL103 will output a”0” to indicate a read operation after the start of the
frame indicator. Following the “10” read signal will be the 5-bit ID address of the PHY device and
the 5-bit register address. Then, the AL103 will cease driving the MDIO line, and wait for one bit
time. During this time, the MDIO should be in a high impedance state. The device will then
synchronize with the next bit of “0” driven by the PHY device, and continue to read 16-bit of data
from the register. The detail timing requirements on PHY management signals are described in the
section “Timing Requirement.”
3.13.2 PHY Management Master Mode
In the master mode, the AL103 will continuously poll the status of the PHY devices through the
serial management interface. The device will also configure the PHY capability fields to ensure
proper operation of the link.
The configuration of the link is automatic. The link capability is programmed by the AL103
through the port configuration register. The AL103 reads from the standard IEEE PHY registers to
determine the auto-negotiated operating speed and mode. If there is a need to manually set the
operation mode because of flow control and cabling issues the AL103 can set the port operation
mode through the MDIO interface (see EEPROM section for programming the AL103).
3.13.3 PHY Management Slave Mode
In the slave mode, the PHY controls the programming of the operating mode. The AL103 will
continuously poll the status of the PHY devices through the serial management interface to
determine the operation mode of the link.
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Reference Only / Allayer Communications
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