AL103 Revision 1.0
Table 9: SGRAM Interface (Continued)
PBA7
PBA6
PBA5
PBA4
PBA3
PBA2
PBA1
PBA0
235
236
237
238
240
241
242
243
O
SGRAM address line PBA0- PBA8 are sampled during the
ACTIVE command (row address) and READ/WRITE command
(column address with PBA8 defining auto precharge).
PBCS#
251
O
Chip Select. Enables and disables the command decoder of
the SGRAM.
PBRAS#
PBCAS#
PBWE#
PBCLKI
245
250
249
195
O
O
O
O
SGRAM Row Address Strobe.
SGRAM Column Address Strobe.
Write Enable.
System Clock Output to Drive the SGRAM.
Table 10: EEPROM Interface
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
EEDIO
EECLK
252
253
I/O EEPROM Serial Data Input and Output.
EEPROM Serial Clock.
O
Table 11: MII PHY Management Interface
PIN
NAME
PIN
NUMBER
I/O
DESCRIPTION
PHY Management Clock.
MDC
93
94
O
MDIO
I/O PHY Management Data Input and Output.
9/00
Reference Only / Allayer Communications
13
ABC [ ABC Taiwan Electronics Corp ]
