Index
A
MII Interface Port 3 9
MII Interface Port 4 9
MII Interface Port 5 10
Address Aging 19
Address Learning 19
AL103 Interface Block Diagram 15
AL103 Overview 5
MII Interface Port 6 10
MII Interface Port 7 11
AL103 Pin Diagram (Top View) 6
Appendix I (VLAN Mapping Worksheet) 61
Appendix II (Port to Trunk Port Assignment Work Sheet) 62
Appendix III (Suggested Memory Components) 63
MII PHY Management Interface 13
MII Receive Timing 51
MII Transmit Timing 51
Miscellaneous Pins 14
Miscellaneous Register (Register 2D) 46
B
Broadcast Storm Control 17
N
Non Auto-negotiation Mode 29
C
Check Sum (Register 47) 50
O
Other PHY Options 29
D
Data Reception 16
P
DC Electrical Characteristics 59
PHY Management 28
PHY Management (MDIO) Read Timing 52
PHY Management (MDIO) Write Timing 53
PHY Management Master Mode 28
PHY Management MDIO 28
PHY Management Slave Mode 28
Pin Descriptions 7
E
EEPROM Interface 13, 29
EEPROM Map 32
EEPROM Read Cycle 31
EEPROM Start and Stop Bit 30
EEPROM Write Cycle 30
Port Aggregation 21
Port Based Trunk Load Balancing 22
Port Configuration Register II 44
Port Configuration Registers (Registers 0D to 1C) 43
F
False Carrier Events 16
Flow Control 25
Port Monitoring 27
Frame Filtering 16
Port Monitoring Configuration (Register 06) 43
Port Operation Status Registers (Register 3A to 41) 47
Port Trunk Port Assignment Registers (Registers 2E to 35) 46
Port VLAN Map Registers (Registers 1E to 2C) 45
Power Interface 14
Frame Forwarding 17
Frame Generation 18
Frame Transmission 18
Full Duplex Flow Control (802.3X) 26
Functional Description 16
Product Description 1
H
Q
Half Duplex Flow Control (Backpressure) 25
Half Duplex Mode Operation 18
Queue Management 26
R
I
Recommended Operation Conditions 59
Register Tables Summary 36
Illegal Frame Length 16
Indirect Resource Access Command Register (Register 42) 49
Indirect Resource Access Data I Register (Register 43) 50
Indirect Resource Access Data II Register (Register 44) 50
Indirect Resource Access Data III Register (Register 45) 50
Indirect Resource Access Data IV Register (Register 46) 50
Reprogramming the EEPROM Configuration 31
Reserved Register (Register 03) 42
Reserved Registers (Registers 07 to 0C) 43
S
Secure Mode Operation 18
L
SGRAM Interface 12, 36
SGRAM Read Timing 55
SGRAM Refresh Timing 53
Load Balancing 21
Long Frames 16
SGRAM Write Timing 57
Static Address Entry Format for EEPROM 32
System Block Diagram 1
System Configuration Register I (Register 00) 39
System Configuration Register II (Register 01) 40
System Configuration Register III (Register 02) 41
System Initialization 29
M
MAC Based Load Balancing Set Up 24
Maximum Ratings 59
Media Independent Interface (MII) 28
MII Interface Port 0 7
MII Interface Port 1 7
MII Interface Port 2 8
Reference Only / Allayer Communications
ABC [ ABC Taiwan Electronics Corp ]
