AL103 Revision 1.0
MXTXD3
MXTXD2
MXTXD1
MXTXD0
MXTXEN
MXTXCLK
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
10/100 MAC
Switch
Controller
MXRXD3
MXRXD2
Address
Control
MXRXD1
MXRXD0
MXRXDV
MXRXCLK
MXRXER
MXCRS
MXCOL
High Speed
Switch Fabric
Address
Table
32
9
PBD[n]
PBA[n]
PBBA
PBCS
PBRAS
PBCAS
PBWE
PBDSF
PBDQM
PBCLK
MDIO
MDC
PHY
Management
Buffer
Manager
Management
Information
EEDIO
EECLK
EEPROM
Interface
RESET
Figure 3
AL103 Interface Block Diagram
9/00
Reference Only / Allayer Communications
15