AAT4900
Buffered Power Half-Bridge
The quiescent current was first measured over
temperature for various input voltages with no load
attached. Equation 7 was then used to derive the
maximum gate charge capability for the desired
maximum junction temperature. QG is the gate
charge required to raise the gate of the load MOS-
FET to the input voltage. This value is taken from
the MOSFET manufacturer's gate charge curve.
Gate Drive
When used as a MOSFET gate driver, the break-
before-make shoot-through protection significantly
reduces losses associated with the driver at high
frequencies. (See Figure 2.)
The low RDS(ON) of the output stage allows for a
high peak gate current and fast switching speeds.
A small package size facilitates close placement to
the power device for optimum switching perform-
ance. The logic level inputs (CLK and EN) are high
impedance inputs.
No Load Operating Current at 85°C Ambient
100
VIN = 4.2V
Gate Drive Current Ratings
VIN = 5.0V
An estimate of the maximum gate drive capability
with no external series resistor can be derived from
Equation 7. Note that the quiescent current varies
with the ambient temperature, frequency of opera-
tion, and input voltage. The graphs below display
the quiescent current and maximum gate charge
drive capability at 85°C ambient vs. frequency for
various input voltages.
10
VIN = 5.5V
VIN = 2.7V
1
0.1
100
1000
10000
Frequency(kHz)
1
FS
TJ(MAX) - TAMB
· VIN(MAX)
JA
⎛
⎝
⎞
Maximum Gate Charge Load @ 85°C
Eq. 7:
QG(MAX)
=
=
·
- IQ
θ
⎠
(Ambient TJ(MAX) = 120°C)
1
120°C - 85°C
⎛
⎞
⎠
1000
·
- 3.2mA
1MHz 190°C/W
·
4.2V
⎝
VIN = 2.7V
VIN = 4.2V
= 40nC
100
10
1
VIN = 5.0V
VIN = 5.5V
100
1000
10000
Frequency (kHz)
+5V
IN
Load
Circuit
Enable
EN
AAT4900
LX
Clock
CLK
GND
Ground
Figure 2: AAT4900 Gate Drive Configuration.
4900.2006.05.1.3
9
AAT [ ADVANCED ANALOG TECHNOLOGY, INC. ]
