AAT4625
USB Single-Channel Power Switch
Refer to the following guidelines for power port
PCB layout:
tor should be kept as short as possible to min-
imized trace resistance and the associated
voltage drop (I2R loss).
1. PCB traces should be kept as short and direct
as possible to minimize the effects of the PCB
on circuit performance.
2. Make component solder pads large to mini-
mize contact resistance.
3. The AAT4625 output bulk capacitor and ferrite
beads should be placed as close to the device
as possible. PCB traces to the output connec-
4. If ferrite beads are used in the circuit, select fer-
rite beads with a minimum series resistance.
5. The use of PCB trace vias should be avoided
on all traces that conduct high currents. If vias
are necessary, make the vias as large as pos-
sible and use multiple vias connected in paral-
lel to minimize their effect.
Ferrite Bead
and PCB Trace
Resistance
0.02Ω
Cable, Connector,
and Contact
Resistance
0.03Ω
P-Channel MOSFET
Switch On Resistance
0.06Ω
Trace Resistance
0.01Ω
(30mV)
(5mV)
(10mV)
(15mV)
V+
VBUS
Downstream
Input
Peripheral Port
Power Supply
4.50V to 5.25V
CBULK
0.1μF
CBULK
0.1μF
500mA Max.
Load Current
AAT4625
GND
GND
(5mV)
(15mV)
(10mV)
Total Voltage Drop = 60mV
Figure 3: Summary of Typical Circuit Voltage Drops Caused by AAT4625
Circuit Components and PCB Trace Resistance.
example for good application layouts. Note that
ferrite beads are not used on this simple device
evaluation board. The board layout shown is not
to scale.
Evaluation Board Layout
The AAT4625 evaluation layout (shown in Figures
4, 5, and 6) follows the recommend printed circuit
board layout procedures and can be used as an
Figure 4: Evaluation Board
Component Side Layout.
Figure 5: Evaluation Board
Solder Side Layout.
Figure 6: Evaluation Board
Top Side Silk Screen Layout/
Assembly Drawing.
4625.2006.04.1.2
11
AAT [ ADVANCED ANALOG TECHNOLOGY, INC. ]
