AAT3532
MicroPower™ Microprocessor Reset Circuit
Manual Reset
The PBRST pin makes it possible to manually
reset the system by either directly connecting a
mechanical push-button between the PBRST pin
and GND or connecting to a logic low output.
Internal de-bounce circuitry is provided to reduce
the effect of noise glitches at the input. The signal
should remain low for a minimum of 20ms for cor-
rect operation. Once the PBRST signal is released
(or goes to a logic high), RESET (RESET) remains
asserted for a minimum of 250ms.
t
PB
t
PBD
PBRST
t
RST
RESET
RESET
Figure 2: Push-Button Reset.
Watchdog Timer
The watchdog timer monitors the microprocessor
to ensure that the system is functioning correctly.
The ST pin of the AAT3532 can be derived from the
microprocessor data signals, address signals,
and/or I/O signals. The watchdog timer function
forces the RST and RST signals into the active
state when the ST input is not toggled by a pre-
determined time. This time period is set by the logic
state of the TD pin, as shown in Table 1. The timer
starts once the RST signals become inactive. If the
watchdog timer does not receive a high-to-low tran-
sition within the specified timeout period, then the
RST signals are activated for a minimum 250ms. In
normal operation, the timer should receive a transi-
tion from the microprocessor within the timeout
period, in which case the timer is reset and normal
operation continues.
The AAT3532 will accept and recognize ST pulses
down to a minimum of 20ns wide.
t
ST
ST
t
TD
Figure 3: Watchdog Input.
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3532.2005.12.1.2
AAT [ ADVANCED ANALOG TECHNOLOGY, INC. ]
