AAT3236
300mA CMOS High Performance LDO
The power dissipation for 500mA load occurring for
8.2% of the duty cycle will be 37mW. Finally, the two
power dissipation levels can summed to determine
the total true power dissipation under the varied load.
High Peak Output Current Applications
Some applications require the LDO regulator to
operate at a continuous nominal level with short
duration, high-current peaks. The duty cycles for
both output current levels must be taken into
account. To do so, first calculate the power dissi-
pation at a nominal continuous level and then factor
in the additional power dissipation due to the short
duration, high-current peaks.
PD(total) = PD(100mA) + PD(500mA)
PD(total) = 83.2mW + 37mW
PD(total) = 120.2mW
The maximum power dissipation for the AAT3236
operating at an ambient temperature of 25°C is
526mW. The device in this example will have a
total power dissipation of 120.2mW. This is well
within the thermal limits for safe operation of the
device.
For example, a 3.3V system using an AAT3236IGV-
3.3-T1 operates at a continuous 100mA load current
level and has short 500mA current peaks. The cur-
rent peak occurs for 378µs out of a 4.61ms period.
It will be assumed the input voltage is 4.2V.
First, the current duty cycle in percent must be
calculated:
Printed Circuit Board Layout
Recommendations
% Peak Duty Cycle: X/100 = 378µs/4.61ms
% Peak Duty Cycle = 8.2%
In order to obtain the maximum performance from
the AAT3236 LDO regulator, very careful attention
must be considered in regard to the printed circuit
board (PCB) layout. If grounding connections are
not properly made, power supply ripple rejection,
low output self noise, and transient response can
be compromised.
The LDO regulator will be under the 100mA load
for 91.8% of the 4.61ms period and have 500mA
peaks occurring for 8.2% of the time. Next, the
continuous nominal power dissipation for the
100mA load should be determined and then multi-
plied by the duty cycle to conclude the actual
power dissipation over time.
Figure 1 shows a common LDO regulator layout
scheme. The LDO regulator, external capacitors
(CIN, COUT and CBYP), and the load circuit are all
connected to a common ground plane. This type of
layout will work in simple applications where good
power supply ripple rejection and low self noise are
not a design concern. For high performance appli-
cations, this method is not recommended.
PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND
)
PD(100mA) = (4.2V - 3.3V)100mA + (4.2V x 150µA)
PD(100mA) = 90.6mW
PD(91.8%D/C) = %DC x PD(100mA)
PD(91.8%D/C) = 0.918 x 90.6mW
PD(91.8%D/C) = 83.2mW
The problem with the layout in Figure 1 is that the
bypass capacitor and output capacitor share the
same ground path to the LDO regulator ground pin,
along with the high-current return path from the load
back to the power supply. The bypass capacitor
node is connected directly to the LDO regulator
internal reference, making this node very sensitive
to noise or ripple. The internal reference output is
fed into the error amplifier, thus any noise or ripple
from the bypass capacitor will be subsequently
amplified by the gain of the error amplifier. This
effect can increase noise seen on the LDO regulator
output, as well as reduce the maximum possible
power supply ripple rejection. There is PCB trace
impedance between the bypass capacitor connec-
The power dissipation for 100mA load occurring for
91.8% of the duty cycle will be 83.2mW. Now the
power dissipation for the remaining 8.2% of the
duty cycle at the 500mA load can be calculated:
PD(MAX) = (VIN - VOUT)IOUT + (VIN x IGND
)
PD(500mA) = (4.2V - 3.3V)500mA + (4.2V x 150µA)
PD(500mA) = 450.6mW
PD(8.2%D/C) = %DC x PD(500mA)
PD(8.2%D/C) = 0.082 x 450.6mW
PD(8.2%D/C) = 37mW
3236.2007.03.1.4
13
AAT [ ADVANCED ANALOG TECHNOLOGY, INC. ]
