DATA SHEET
AAT2822/2823/2824/2825
TFT-LCD DC/DC Converter with WLED Driver and VCOM Buffer
gested value for R3 is 6.04kΩ. The resistive divider can
be calculated in the following equation:
decade lower than the frequency of RHP zero to guaran-
tee the loop stability. A series capacitor and resistor
network (R11 and C8) connected to the COMP pin sets
the pole and zero which are given by:
VAVDD
VFB
V
R3 = R2 ·
-1 = R2 ·
AVDD - 1
0.6V
1
fP_COM
=
2π · REA · C8
R3 = 6.04kΩ
R2 (kΩ)
R3 = 59kΩ
R2 (MΩ)
VAVDD (V)
1
fZ_COM
=
9
84.5
93.1
105
115
124
143
196
215
237
0.825
0.931
1.02
1.13
1.21
1.4
1.1
2.1
2.3
2π · R11 · C8
10
11
12
13
15
20
22
24
Where:
C8 is the compensation capacitor
R11 is the compensation resistor
REA is the output resistance of the error amplifier (MΩ).
A 100pF capacitor and a 200kΩ resistor in series are
chosen for optimum phase margin and fast transient
response.
Table 1: Setting the Output Voltage
for the Main Step-Up Converter.
Charge Pump
Selecting Compensation Components
The number of charge pump stages required for a given
output (VGH) varies with the input voltage applied (VAVDD
)
The AAT2822 main boost architecture uses peak current
mode control to eliminate the double pole effect of the
output L&C filter and simplifies compensation loop
design. The current mode control architecture simplifies
the transfer function of the control loop to a one-pole,
one left plane zero and one right half plane (RHP) sys-
tem in frequency domain. The dominant pole can be
calculated by:
from the main boost. A lower input voltage requires
more stages for a given output. If the numbers of stag-
es increases, the maximum load current limitation of the
charge pump would be decreased to maintain output
voltage regulation.
The number of stages required can be estimated by:
VGH - VAVDD(MIN)
nP =
1
fP =
VAVDD(MIN) - 2VF
2π · RO · C6
for the positive output and
The ESR zero of the output capacitor can be calculated
by:
VGL
nN =
1
2VF - VAVDD(MIN)
fZ_ESR
=
2π · RESR · C6
for the negative output where VF = 0.31V is the forward
voltage of the BAT54 Schottky diode at 4mA forward
current.
Where:
C6 is the output filter capacitor
RO is the load resistor value
RESR is the equivalent series resistance of the output
capacitor.
When solving for np and nn, round up the solution to the
next highest integer to determine the number of stages
required.
The right half plane (RHP) zero can be determined by:
Negative Output Voltage (VGL)
2
VIN
The negative output voltage is adjusted by a resistive
divider from the output (VON) to the FBN and REF pins.
The maximum reference voltage current is 200µA;
therefore, the minimum allowable value for R10 of Figure
fZ_RHP
=
2π · L1 · IAVDD · VAVDD
It is recommended to design the bandwidth to one
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