AC Electrical Characteristics † - Processor Bus (Figures 11 and 17)
Characteristics
Sym
Min Typ ‡ Max
Units
ns
Test Conditions
1
2
3
4
Chip Select Setup Time
Read/Write Setup Time
Address Setup Time
tCSS
20
25
25
40
2.7
20
0
5
5
t
RWS
ns
t
ADS
ns
A
cknowledgement
Fast
t
AKD
100
7.2
ns
CL=150 pF
Delay
Slow
t
AKD
cycles
ns
C4i cycles ➀
5
6
7
8
Fast Write Data Setup Time
Slow Write Data Delay
Read Data Setup Time
Data Hold Time Read
Write
t
FWS
SWD
RDS
t
2.0
1.7
0.5
cycles C4i cycles ➀
t
cycles C4i cycles ➀, CL= 150 pF
t
DHT
DHT
RDZ
20
20
ns
ns
ns
ns
ns
ns
ns
RL=1 KΩ * , CL=150 pF
t
10
50
9
Read Data To High Imp.
t
t
90
RL=1 KΩ * , CL=150 pF
10 Chip Select Hold Time
11 Read/Write Hold Time
12 Address Hold Time
13 Acknow. Hold Time
t
CSH
0
0
RWH
t
ADH
AKH
0
t
10
60
80
RL=1 KΩ * , CL=150 pF
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
High Impedance is measured by pulling to the appropriate rail with R L, with timing corrected to cancel time taken to discharge C L.
*
➀ Processor accesses are dependent on the C4i clock, and so some timings are expressed as multiples of the C4i clock period.
Figure 17 Processor Bus
2.0V
0.8V
DS
2.0V
CS
0.8V
t
t
CSS
CSH
2.0V
0.8V
R/W
t
t
RWS
RWH
2.0V
0.8V
A5
to
A0
t
t
ADH
ADS
t
AKD
t
AKH
2.4V
0.4V
DTA
t
RDS
t
DHT
D7
to
D0
2.4V (Read) 2.0V (Write)
0.8V (Read) 0.8V (Write)
t
t
t
SWD
FWS
RDZ
11
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