IMP811, IMP812
Detailed Description
Reset Timing and Manual Reset (MR)
The reset signal is asserted–LOW for the IMP811 and HIGH for
the IMP812 – when the VCC signal falls below the threshold trip
voltage and remains asserted for 140ms minimum after the VCC
has risen above the threshold.
MR may be connected to a normally-open switch connected to
ground without an external debounce circuit.
For added noise rejection, a 0.1µF capacitor from MR to Ground
can be added.
A logic low on MR asserts RESET LOW on the IMP811 and HIGH
on the IMP812. MR is internally pulled high through a 20kΩ
resistor and can be driven by TTL/CMOS gates or with open
collector/drain outputs. MR can be left open if not used.
5V
VCC
VTH
0V
Active Reset
Timeout Period
140ms
minimum
5V
MR
Active Reset
0V
Timeout Period
5V
0V
RESET
RESET
IMP811
5V
0V
IMP812
811/12_03.eps
Figure 1. Reset Timing and Manual Reset (MR)
5
A1PROS [ A1 PROS CO., LTD. ]
