IMP706P/R/S/T/J, IMP708R/S/T/J
Detail Descriptions
width is 0.5µs with a 3V VCC input and 0.15µs with a 5V VCC
input. If not used, tie MR to VCC or leave floating.
RESET/RESET Operation
The RESET/RESET signals are designed to start or return a
µP/µC to a known state.
By connecting the watchdog output (WDO) and MR, a watchdog
timeout forces a RESET to be generated.
With VCC above 1.2V, RESET and RESET are guaranteed to be
asserted. During a power-up sequence, the reset outputs remain
asserted until the supply rises above the threshold level. The
resets are deasserted approximately 200ms after crossing the
threshold.
Watchdog Timer
A watchdog timer available on the IMP706P/R/S/T/J monitors
µP/µC activity. If activity is not detected within 1.6 seconds on the
Watchdog Input (WDI), the internal timer puts the Watchdog
Output (WDO) into a LOW state. WDO will remain LOW until
activity is detected at WDI.
In a brownout situation where VCC falls below the threshold level,
the reset outputs are asserted. If a brownout occurs during an
already initiated reset period, the reset period will extend for an
additional reset period of 200ms.
The watchdog function is disabled, meaning it is cleared and not
counting, if WDI is floated or connected to a three-stated circuit.
The watchdog timer is also disabled if RESET is asserted. When
RESET becomes inactive and the WDI input sees a high or low
transition as short as 100ns (VCC = 2.7V)/50ns (VCC = 4.5V), the
watchdog timer will begin a 1.6 second countdown. Additional
transitions at WDI will reset the watchdog timer and initiate a
new countdown sequence.
The IMP708 devices have dual reset outputs, one active LOW and
one active HIGH. The IMP706P has a single active HIGH reset and
the IMP706/R/S/T/J devices have an active LOW reset output.
IMP Part RESET Polarity Threshold Watchdog Timer
IMP706P
IMP706R
IMP706S
IMP706T
IMP706J
IMP708R
IMP708S
IMP708T
IMP708J
HIGH
2.63V
2.63V
2.93V
3.08V
4.00V
2.63V
2.93V
3.08V
4.00V
Yes
Yes
Yes
Yes
Yes
No
LOW
WDO will also become LOW and remain so, whenever the supply
voltage, VCC, falls below the device threshold level. WDO goes HIGH
as soon as VCC transitions above the threshold. There is no minimum
pulse width for WDO as there is for the RESET outputs. If WDI is float-
ed, WDO essentially acts as a low supply voltage output indicator.
LOW
LOW
LOW
Both: HIGH & LOW
Both: HIGH & LOW
Both: HIGH & LOW
Both: HIGH & LOW
No
Power-failure detection with auxiliary comparator
No
All devices have an auxiliary comparator with 1.25V trip point.
The output, PFO, is active LOW and the noninverting input is PFI.
This comparator can be used as a supply voltage monitor with an
external resistor voltage divider. As the monitored voltage level
falls, PFI is reduced causing the PFO output to go LOW.
Normally PFO interrupts the processor so the system can be shut
down in a controlled manner.
No
Manual Reset (MR)
The active-LOW manual reset input is pulled high by an internal
20kΩ pull-up resistor and can be driven low by CMOS/TTL logic
or a mechanical switch to ground. An external debounce circuit is
unnecessary since the 140ms minimum reset time will debounce
mechanical pushbutton switches. The minimum MR input pulse
5V
vRT
V
CC
0V
tRS
tRS
5V
0V
5V
WDI
RESET
0V
tWD
tWD
tWP
5V
0V
5V
0V
MR externally
set low
MR
WDO
tMD
tWD
tMR
5V
0V
5V
0V
WDO
RESET
RESET triggered by MR
706P_04.eps
706P_05.eps
Watchdog Timing
WDI Three-state operation
408-432-9100/www.impweb.com
© 1999 IMP, Inc.
6
A1PROS [ A1 PROS CO., LTD. ]
