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IMP1832SEMA 参数 Datasheet PDF下载

IMP1832SEMA图片预览
型号: IMP1832SEMA
PDF下载: 下载PDF文件 查看货源
内容描述: 3..3V μP电源Supplly Moniittor和Ressett Ciircuiitt [3..3V μP Power Supplly Moniittor and Ressett Ciircuiitt]
分类和应用:
文件页数/大小: 7 页 / 111 K
品牌: A1PROS [ A1 PROS CO., LTD. ]
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IMP1 832
Application Information
Supply Voltage Monitor
The IMP1832 monitors the microprocessor or microcontroller
power supply and issues reset signals, both active HIGH and
active LOW, that halt processor operation whenever the power
supply voltage levels are outside a predetermined tolerance.
Tolerance levels are set with the TOL pin.
RESET and RESET signals are generated at the last moment of a
valid V
CC
signal. On power-up, both reset signals are active for a
minimum of 250ms after the supply has returned to intolerance
level. This allows the power supply and monitored processor to
stabilize before instruction execution is allowed to begin.
Trip Point Tolerance Selection
With TOL connected to V
CC
, RESET and RESET become active
whenever V
CC
falls below 2.64V. RESET and RESET become active
when V
CC
falls below 2.98V if TOL is connected to ground.
After V
CC
has risen above the trip point set by TOL, RESET and
RESET remain active for a minimum time period of 250ms.
On power-down, once V
CC
falls below the reset threshold RESET
stays LOW and is guaranteed to be 0.4V or less until V
CC
drops
below 1.2V. The active HIGH reset signal is valid down to a V
CC
level of 1.2V also.
Tolerance
Select
TOL = V
CC
TOL = GND
TRIP Point Voltage (V)
Tolerance
20%
10%
Min
2.47
2.80
Nominal
2.55
2.88
Max
2.64
2.97
1832 t02.eps
Manual Reset Operation
Push-button switch input, PBRST, allows the user to override the
internal trip point detection circuits and issue reset signals. The
pushbutton input is debounced and is pulled HIGH through an
internal 40kΩ resistor.
When PBRST is held LOW for the minimum time t
PB
, both resets
become active and remain active for a minimum time period of
250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses greater
than 20ms. No external pull-up resistor is required, since PBRST
is pulled HIGH by an internal 40kΩ resistor.
The PBRST can be driven from a TTL or CMOS logic line or short-
ed to ground with a mechanical switch.
t
R
V
CCTP(MAX)
V
CCTP
V
CCTP(MIN)
V
CC
t
RPU
RESET
V
OH
V
IL
V
OL
RESET
1832_04.eps
PBRST
t
PB
t
PDLY
V
IH
t
RST
RESET
RESET
V
OH
V
OL
1832_07.eps
Figure 1. Timing Diagram: Power Up
t
F
V
CC
V
CCTP(MAX)
V
CCTP
Figure 3. Timing Diagram: Pushbutton Reset
Supply
Voltage
IMP1832
1
PBRST
TD
TOL
GND
V
CC
ST
RESET
RESET
8
7
6
5
µP
V
CCTP(MIN)
RESET
t
RPD
2
3
RESET
V
OH
V
OL
1832_03.eps
4
RESET
1832_05.eps
Figure 2. Timing Diagram: Power Down
4
Figure 4. Application Circuit: Pushbutton Reset
©
1999 IMP, Inc.
408-432-9100/www.impweb.com