Ai329CA
BIAS CONDITION
Parameter
Output amplifier drain voltage
Substrate voltage adjustment range
Fluctuation range after substrate voltage adjustment
Reset gate clock voltage adjustment range
Fluctuation range after reset gate voltage adjustment
Protection bias
Symbol
V
DD
V
SUB
△V
SUB
V
RG
△V
RG
V
P
Min
14.5
5
–1
0
–3
Typ
15.0
Max
15.5
15
1
4
3
Unit
V
V
V
V
%
Remark
*
Set to low level
of vertical transfer clock
* No adjustment of reset gate clock voltage is necessary when reset gate clock is driven as indicated below.
Parameter
Reset gate clock voltage
V
RG
8.5
9.0
9.5
V
Symbol
V
RGL
Min
–0.2
Typ
0.0
Max
0.2
Unit
V
Remarks
DC CHARACTERISTICS
Parameter
Output amplifier drain current
Symbol
I
DD
Min
–
Typ
3
Max
–
Unit
㎃
DRIVING CONDITION
Parameter
Vertical clock high voltage
Vertical clock middle voltage
Vertical clock low voltage
Horizontal clock high voltage
Horizontal clock low voltage
RG clock voltage difference
Substrate clock voltage
Symbol
V
H1
, V
H3
V
M1, 2, 3, 4
V
L1, 2, 3, 4
H
H1, 2
H
L1, 2
RG
HL
V
SUB
Min
14.5
–0.2
–9.0
4.5
–0.5
4.7
23
Typ
15.0
0.0
–8.5
5.0
0.0
5.0
24
Max
15.5
0.2
–8.0
5.5
0.5
5.3
25
Unit
V
V
V
V
V
V
V
3