Advanced Power
Electronics Corp.
FEATURES
Ideal for DDR-I, DDR-II and DDR-III V
TT
Applications
Sink and Source 2A Continuous Current
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL_18,
HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in ESOP-8 (Exposed Pad) & SO-8 Packages
V
IN
and V
CNTL
No Power Sequence Issue
RoHS Compliant and 100% Lead (Pb)-Free
AP1280
DESCRIPTIOON
The AP1280 is a simple, cost-effective and high-
speed linear regulator designed to generate termination
voltage in double data rate (DDR) memory system to
comply with the JEDEC SSTL_2 and SSTL_18 or other
specific interfaces such as HSTL, SCSI-2 and SCSI-3
etc. devices requirements. The regulator is capable of
actively sinking or sourcing up to 2A while regulating an
output voltage to within 40mV. The output termination
voltage cab be tightly regulated to track 1/2V
DDQ
by two
external voltage divider resistors or the desired output
voltage can be pro-grammed by externally forcing the
REFEN pin voltage.
The AP1280 also incorporates a high-speed
differential amplifier to provide ultra-fast response in
line/load transient. Other features include extremely low
initial offset voltage, excellent load regulation, current
limiting in bi-directions and on-chip thermal shut-down
protection.
The AP1280 are available in the ESOP-8
(Exposed Pad) & SO-8 surface mount packages.
2A SINK/SOURCE BUS TERMINATION REGULATOR
APPLICATION
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
TYPICAL APPLICATION
VCNTL=3.3V
VIN=2.5V/1.8V/1.5V
C
IN
R
1
2N7002
EN
C
SS
R
2
GND
VIN
VCNTL
C
CNTL
R
TT
AP1280
REFEN
VOUT
C
OUT
R
DUMMY
R
1
= R
2
= 100KΩ, R
TT
= 50Ω / 33Ω / 25Ω
C
OUT,min
= 10uF (Ceramic) + 100uF under the worst case testing condition
C
SS
= 1µF, C
IN
= 470µF(Low ESR), C
CNTL
= 47µF
Data and specifications subject to change without notice
1
201003052