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AP1250CMP 参数 Datasheet PDF下载

AP1250CMP图片预览
型号: AP1250CMP
PDF下载: 下载PDF文件 查看货源
内容描述: 2A SINK / SOURCE总线终端稳压器 [2A Sink/Source Bus Termination Regulator]
分类和应用: 稳压器
文件页数/大小: 5 页 / 414 K
品牌: A-POWER [ ADVANCED POWER ELECTRONICS CORP. ]
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Advanced Power
Electronics Corp.
2A Sink/Source Bus Termination Regulator
Description
The
AP1250CMP
is a simple, cost-effective and
high-speed linear regulator designed to generate
termination voltage in double data rate (DDR)
memory system to comply with the JEDEC SSTL_2
and SSTL_18 or other specific interfaces such as
HSTL,
SCSI-2
and
SCSI-3
etc.
devices
requirements. The regulator is capable of actively
sinking or sourcing up to 2A while regulating an
output
voltage
to
within
40mV.
The
output
termination voltage cab be tightly regulated to track
1/2V
DDQ
by two external voltage divider resistors or
the desired output voltage can be pro-grammed by
externally forcing the REFEN pin voltage.
The
AP1250CMP
also incorporates a high-speed
differential amplifier to provide ultra-fast response in
line/load transient. Other features include extremely
low initial offset voltage, excellent load regulation,
current limiting in bi-directions and on-chip thermal
shut-down protection.
The
AP1250CMP
are available in the
ESOP-8
(Exposed Pad) surface mount packages.
AP1250CMP
Features
Ideal for DDR-I, DDR-II and DDR-III V
TT
Applications
Sink and Source 2A Continuous Current
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2, SSTL
_18, HSTL, SCSI-2 and SCSI-3 Interfaces.
High Accuracy Output Voltage at Full-Load
Output Adjustment by Two External Resistors
Low External Component Count
Shutdown for Suspend to RAM (STR) Functionality
with High-Impedance Output
Current Limiting Protection
On-Chip Thermal Protection
Available in
ESOP-8
(Exposed Pad) Packages
V
IN
and V
CNTL
No Power Sequence Issue
RoHS Compliant and 100% Lead (Pb)-Free
Application
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs, Printers
Embedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
Pin Configuration
ESOP-8 (MP)
(Top View)
VIN
GND
REFEN
VOUT
Block Diagram
NC
NC
VCNTL
NC
1
8
2
7
GND
3
6
4
5
Pin Description
Pin Name
V
IN
GND
V
CNTL
REFEN
V
OUT
Power Input
Ground
Gate Drive Voltage
Reference Voltage input and Chip Enable
Output Voltage
Pin function
1
200901074