V-Data
VDS7616A4A
AC Characteristics
Speed
-6
-5.5
Max
-7
Parameter
Symbol
Unit
Note
Min
5.5
7.5
2
Min
Max
Min
7
Max
/CAS Latency = 3 tCK3
/CAS Latency = 2 tCK2
6
System clock
Cycle time
1000
1000
1000
ns
7.5
7.5
2.5
2.5
-
-
-
2
2
-
-
Clock high pulse width
Clock low pulse width
tCHW
tCLW
-
ns
ns
1
1
2
-
-
5
-
5
/CAS Latency = 3 tAC3
/CAS Latency = 2 tAC2
5.4
Access time form
clock
ns
2
-
5.4
-
-
5.4
-
-
5.4
57
57
/RAS cycle time Operation
/RAS to /CAS delay
/RAS active time
tRC
57
15
42
15
1
--
ns
ns
15
42
15
1
-
15
42
15
1
-
tRCD
tRAS
tRP
-
100K
100K
100K
ns
-
-
-
-
/RAS precharge time
/CAS to /CAS delay
DQM to data – in mask
Data – out hold time
Data – input setup time
Data – input hold time
Address setup time
Address hold time
-
-
ns
tCCD
tDQM
tOH
CLK
CLK
ns
0
-
0
-
0
-
2.75
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
2.75
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
3
-
-
-
tDS
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
1
-
ns
1
1
1
1
1
1
1
1
-
-
tDH
-
ns
-
-
tAS
-
ns
-
-
tAH
-
ns
-
-
CKE setup time
tCKS
tCKH
tCMS
tCMH
tOLZ
tMRD
tPDE
tSRE
tREF
-
ns
-
-
CKE hold time
-
ns
-
-
Command setup time
Command hold time
CLK to data output in low Z-time
MRS to new command
Power down exit time
Self refresh exit time
Refresh time
-
ns
-
-
-
ns
-
-
-
ns
1
-
1
-
2
-
CLK
CLK
CLK
ms
1
-
1
-
1
-
1
-
1
-
1
-
3
-
64
64
64
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.
2. Access times to be measured with input signals of 1v / ns edge rate.
3.A new command can be given tRRC after self refresh exit.
Rev 1.0 April, 2001
6
ADATA [ ADATA Technology Co., Ltd. ]
