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ADS7608A4A-6 参数 Datasheet PDF下载

ADS7608A4A-6图片预览
型号: ADS7608A4A-6
PDF下载: 下载PDF文件 查看货源
内容描述: 同步DRAM ( 4M ×8位×4银行) [Synchronous DRAM(4M X 8 Bit X 4 Banks)]
分类和应用: 动态存储器
文件页数/大小: 8 页 / 635 K
品牌: ADATA [ ADATA Technology Co., Ltd. ]
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A-Data  
ADS7608A4A  
AC Characteristics  
-5  
-5.5  
-6  
-7  
-7.5  
Parameter  
Symbol  
Unit Note  
Min Max Min Max Min Max Min Max Min Max  
System clock /CAS Latency = 3 tCK3  
Cycle time  
5
10  
2
5.5  
10  
6
10  
2.5  
2.5  
-
7
10  
2.5  
2.5  
-
7.5  
7.5  
2.5  
2.5  
-
1000  
1000  
1000  
1000  
1000 ns  
/CAS Latency = 2 tCK2  
Clock high pulse width  
Clock low pulse width  
tCHW  
tCLW  
-
-
2.25  
2.25  
-
-
-
-
-
-
-
-
ns  
ns  
1
1
2
-
5.4  
5.4  
-
Access time /CAS Latency = 3 tAC3  
-
4.5  
6
-
5
6
-
5.4  
6
-
5.4  
6
-
ns  
2
form clock  
/RAS cycle  
time  
/CAS Latency = 2 tAC2  
-
-
-
-
-
Operation  
tRC  
55  
55  
15  
55  
60  
60  
18  
62  
62  
20  
65  
65  
15  
ns  
ns  
Auto Refresh  
tRRC  
tRCD  
tRAS  
tRP  
-
55  
-
-
-
-
/RAS to /CAS delay  
-
16.5  
-
-
-
-
/RAS active time  
40 100K 38.5 100K 42 100K 42 120K 45 120K ns  
/RAS precharge time  
/RAS to /RAS bank active delay  
/CAS to /CAS delay  
15  
10  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16.5  
11  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
18  
12  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
20  
14  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15  
15  
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns  
ns  
tRRD  
tCCD  
CLK  
CLK  
CLK  
CLK  
CLK  
CLK  
ns  
Write command to data – in delay tWTL  
Data – in to precharge command tDPL  
0
0
0
0
0
1
1
1
1
1
Data – in active command  
DQM to data – out Hi-Z  
DQM to data – in mask  
Data – out hold time  
Data – input setup time  
Data – input hold time  
Address setup time  
Address hold time  
tDAL  
tDQZ  
tDQM  
tOH  
5
5
5
4
4
2
2
2
2
2
0
0
0
0
0
1.5  
1.5  
1
2
2.7  
1.5  
1
2.7  
1.5  
1
2.7  
1.5  
1
tDS  
1.5  
1
ns  
1
1
1
1
1
1
1
1
tDH  
ns  
tAS  
1.5  
1
1.5  
1
1.5  
1
1.5  
1
1.5  
1
ns  
tAH  
ns  
CKE setup time  
tCKS  
tCKH  
tCS  
1.5  
1
1.5  
1
1.5  
1
1.5  
1
1.5  
1
ns  
CKE hold time  
ns  
Command setup time  
Command hold time  
CLK to data output in low Z-time  
MRS to new command  
Power down exit time  
Self refresh exit time  
Refresh time  
1.5  
1
1.5  
1
1.5  
1
1.5  
1
1.5  
1
ns  
tCH  
ns  
tOLZ  
tMRD  
tPDE  
tSRE  
tREF  
1
1
1
1.5  
1
1.5  
1
ns  
2
2
2
CLK  
CLK  
CLK  
ms  
1
1
1
1
1
1
1
1
1
1
3
64  
64  
64  
64  
64  
Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.  
2. Access times to be measured with input signals of 1v / ns edge rate.  
3.A new command can be given tRRC after self refresh exit.  
Rev 1 April, 2001  
6