A-Data
ADD8608A8A
8M x 8 Bit x 4 Banks
Double Data Rate SDRAM
General Description
Features
•2.5V for VDDQ power supply
•SSTL_2 interface
The ADD8608A8A are four-bank Double Data
Rate(DDR) Synchronous DRAMs organized as
8,392,608 words x 8 bits x 4 banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
•MRS Cycle with address key programs
-CAS Latency (2, 2.5)
-Burst Length (2,4 &8)
-Burst Type (sequential & Interleave)
•4 banks operation
•Differential clock input (CK, /CK) operation
•Double data rate interface
•Auto & Self refresh
Data outputs occur at both rising edges of CK and
/CK.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
•8192 refresh cycle
•DQM for masking
•Package:66-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
Interface
SSTL_2
Package
ADD8608A8A-75BA
ADD8608A8A-75B
133Mhz(7.5ns/CL=2)
133Mhz(7.5ns/CL=2.5)
400mil 66pin TSOPII
Pin Assignment
VDD
V
S S
6
6
65
4
1
2
3
4
5
6
7
8
9
DQ
0
DDQ
DQ7
V
V
S SQ
6
6
3
6 2
NC
DQ1
NC
DQ6
V
S S Q
V
DDQ
1
6
NC
DQ2
NC
DQ5
60
5 9
5 8
V
DDQ
V
S SQ
NC
DQ3
NC
DQ4
5
1 0
1 1
1 2
1 3
1 4
1 5
1 6
7
5 6
5 5
54
V
S S Q
V
DDQ
NC
NC
V
NC
N C
3
5
5 2
5 1
5 0
4
4
4 7
4 6
4 5
44
DDQ
V
S S Q
NC
NC
DQS
N C
VR E F
VS S
1
7
VDD
1 8
1 9
2 0
9
8
NC1
NC
DM
CK
CK
CKE
NC
A12
A11
A9
21
22
23
24
25
26
27
28
29
3 0
3 1
3 2
3 3
WE
CAS
RAS
CS
NC
43
2
4
BS0
41
40
BS1
A10/AP
A0
A8
39
3 8
3 7
3 6
3 5
A7
A 6
A5
A1
A2
A3
A4
VS S
3
4
VDD
66-pin plastic TSOP II 400 mil
Rev 2 April, 2002
2
ADATA [ ADATA Technology Co., Ltd. ]
