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X24164S8M-2.7 参数 Datasheet PDF下载

X24164S8M-2.7图片预览
型号: X24164S8M-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: 串行E2PROM [Serial E2PROM]
分类和应用: 存储内存集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 14 页 / 62 K
品牌: XICOR [ XICOR INC. ]
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X24164  
DEVICE ADDRESSING  
The last bit of the slave address defines the operation to  
be performed. When set to one a read operation is  
selected, when set to zero a write operation is selected.  
Following a start condition the master must output the  
address of the slave it is accessing. The most significant  
bitoftheslaveisaone(seeFigure4). Thenextthreebits  
are the device select bits. A system could have up to  
eight X24164’s on the bus. The eight addresses are  
definedbythestateoftheS0, S1, andS2 inputs. S1 ofthe  
slave address must be the inverse of the S1 input pin.  
Following the start condition, the X24164 monitors the  
SDA bus comparing the slave address being transmit-  
ted with its slave address device type identifier. Upon a  
correct compare the X24164 outputs an acknowledge  
on the SDA line. Depending on the state of the R/W bit,  
the X24164 will execute a read or write operation.  
Figure 4. Slave Address  
WRITE OPERATIONS  
Byte Write  
HIGH  
ORDER  
DEVICE  
SELECT  
WORD  
ADDRESS  
For a write operation, the X24164 requires a second  
address field. This address field is the word address,  
comprised of eight bits, providing access to any one of  
2048 words in the array. Upon receipt of the word  
address the X24164 responds with an acknowledge,  
and awaits the next eight bits of data, again responding  
with an acknowledge. The master then terminates the  
transferbygeneratingastopcondition,atwhichtimethe  
X24164 begins the internal write cycle to the nonvolatile  
memory. While the internal write cycle is in progress the  
X24164 inputs are disabled, and the device will not  
respond to any requests from the master. Refer to  
Figure5fortheaddress, acknowledgeanddatatransfer  
sequence.  
1
S
S
1
S
0
A2  
A1  
A0 R/W  
2
3846 FHD F10  
Thenextthreebitsoftheslaveaddressareanextension  
of the array’s address and are concatenated with the  
eight bits of address in the word address field, providing  
direct access to the whole 2048 x 8 array.  
Figure 5. Byte Write  
S
T
S
SLAVE  
ADDRESS  
WORD  
ADDRESS  
A
R
T
T
BUS ACTIVITY:  
MASTER  
DATA  
O
P
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:  
X24164  
3846 FHD F11  
5