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X24128S-1.8 参数 Datasheet PDF下载

X24128S-1.8图片预览
型号: X24128S-1.8
PDF下载: 下载PDF文件 查看货源
内容描述: 400kHz的2线串行E2PROM与锁座 [400KHz 2-Wire Serial E2PROM with Block Lock]
分类和应用: 可编程只读存储器
文件页数/大小: 17 页 / 89 K
品牌: XICOR [ XICOR INC. ]
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X24128  
WRITE OPERATIONS  
Byte Write  
master can transmit up to thirty-one more words. The  
device will respond with an acknowledge after the  
receipt of each word, and then the byte address is  
internally incremented by one. The page address  
remains constant. When the counter reaches the end  
of the page, it “rolls over” and goes back to the first  
byte of the current page. This means that the master  
can write 32 words to the page beginning at any byte.  
If the master begins writing at byte 16, and loads 32  
words, then the first 16 words are written to bytes 16  
through 31, and the last 16 words are written to bytes  
0 through 15. Afterwards, the address counter would  
point to byte 16. If the master writes more than 32  
words, then the previously loaded data is overwritten  
by the new data, one byte at a time.  
For a write operation, the device requires the Slave  
Address Byte, the Word Address Byte 1, and the Word  
Address Byte 0, which gives the master access to any  
one of the words in the array. Upon receipt of the Word  
Address Byte 0, the device responds with an acknowl-  
edge, and waits for the first eight bits of data. After  
receiving the 8 bits of the data byte, the device again  
responds with an acknowledge. The master then  
terminates the transfer by generating a stop condition,  
at which time the device begins the internal write cycle  
to the nonvolatile memory. While the internal write  
cycle is in progress the device inputs are disabled  
and the device will not respond to any requests from  
the master. The SDA pin is at high impedance. See  
figure 5.  
The master terminates the data byte loading by  
issuing a stop condition, which causes the device to  
begin the nonvolatile write cycle. As with the byte write  
operation, all inputs are disabled until completion of  
the internal write cycle. Refer to figure 6 for the  
address, acknowledge, and data transfer sequence.  
Page Write  
The device is capable of a thirty-two byte page write  
operation. It is initiated in the same manner as the byte  
write operation; but instead of terminating the write  
operation after the first data word is transferred, the  
Figure 5. Byte Write Sequence  
S
SIGNALS  
FROMTHE  
MASTER  
S
T
A
R
T
WORDADDRESS WORD ADDRESS  
BYTE 1  
SLAVE  
ADDRESS  
T
O
P
BYTE 0  
DATA  
SDA BUS  
S 1 0 1 0  
0
P
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS  
FROMTHE  
SLAVE  
7027 FM 07  
Figure 6. Page Write Sequence  
(0n31)  
S
SIGNALS  
FROMTHE  
MASTER  
T
A
R
T
WORD ADDRESS WORDADDRESS  
BYTE 1  
DATA  
(0)  
DATA  
(n)  
SLAVE  
ADDRESS  
S
T
O
P
BYTE 0  
SDA BUS  
1 0 1 0  
S
0
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
SIGNALS  
FROMTHE  
SLAVE  
7027 FM 08  
6