128K
16K x 8 Bit
X24128
400KHz 2-Wire Serial E2PROM with Block LockTM
FEATURES
DESCRIPTION
2
• Save Critical Data with Programmable
Block Lock Protection
—Block Lock (0, 1/4, 1/2, or all of E PROM Array)
The X24128 is a CMOS Serial E PROM, internally
organized 16K x 8. The device features a serial inter-
face and software protocol allowing operation on a
simple two wire bus.
2
—Software Write Protection
—Programmable Hardware Write Protect
• In Circuit Programmable ROM Mode
• 400KHz 2-Wire Serial Interface
—Schmitt Trigger Input Noise Suppression
—Output Slope Control for Ground Bounce
Noise Elimination
• Longer Battery Life With Lower Power
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
• 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V
Power Supply Versions
Three device select inputs (S –S ) allow up to eight
devices to share a common two wire bus.
0
2
A Write Protect Register at the highest address loca-
tion, FFFFh, provides three write protection features:
Software Write Protect, Block Lock Protect, and
Programmable Hardware Write Protect. The Software
Write Protect feature prevents any nonvolatile writes to
the device until the WEL bit in the Write Protect
Register is set. The Block Lock Protection feature
gives the user four array block protect options, set by
programming two bits in the Write Protect Register.
The Programmable Hardware Write Protect feature
allows the user to install the device with WP tied to
• 32 Word Page Write Mode
—Minimizes Total Write Time Per Word
• Internally Organized 16K x 8
• Bidirectional Data Transfer Protocol
• Self-Timed Write Cycle
V
, write to and Block Lock the desired portions of
CC
the memory array in circuit, and then enable the In
Circuit Programmable ROM Mode by programming the
WPEN bit HIGH in the Write Protect Register. After
this, the Block Locked portions of the array, including
the Write Protect Register itself, are permanently
protected from being erased.
—Typical Write Cycle Time of 5ms
• High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100Years
• 14-Lead SOIC
• 16-Lead SOIC
• 8-Lead PDIP
FUNCTIONAL DIAGRAM
DATA REGISTER
Y DECODE LOGIC
SERIAL E2PROM DATA
AND ADDRESS (SDA)
COMMAND
DECODE
AND
CONTROL
LOGIC
SERIAL E2PROM
SCL
ARRAY
PAGE
16K x 8
DECODE
LOGIC
4K x 8
BLOCK LOCK AND
WRITE PROTECT
CONTROL LOGIC
4K x 8
8K x 8
S2
DEVICE
SELECT
LOGIC
WRITE
PROTECT
REGISTER
S1
S0
WRITE VOLTAGE
CONTROL
WP
7027 FM 01
Xicor, 1995, 1996 Patents Pending
7027-1.3 5/14/97 T2/C0/D2 SH
Characteristics subject to change without notice
1
XICOR [ XICOR INC. ]
