欢迎访问ic37.com |
会员登录 免费注册
发布采购

X24128P-1.8 参数 Datasheet PDF下载

X24128P-1.8图片预览
型号: X24128P-1.8
PDF下载: 下载PDF文件 查看货源
内容描述: 400kHz的2线串行E2PROM与锁座 [400KHz 2-Wire Serial E2PROM with Block Lock]
分类和应用: 存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 17 页 / 89 K
品牌: XICOR [ XICOR INC. ]
 浏览型号X24128P-1.8的Datasheet PDF文件第3页浏览型号X24128P-1.8的Datasheet PDF文件第4页浏览型号X24128P-1.8的Datasheet PDF文件第5页浏览型号X24128P-1.8的Datasheet PDF文件第6页浏览型号X24128P-1.8的Datasheet PDF文件第8页浏览型号X24128P-1.8的Datasheet PDF文件第9页浏览型号X24128P-1.8的Datasheet PDF文件第10页浏览型号X24128P-1.8的Datasheet PDF文件第11页  
X24128  
READ OPERATIONS  
Acknowledge Polling  
The maximum write cycle time can be significantly  
reduced using Acknowledge Polling. To initiate  
Acknowledge Polling, the master issues a start condi-  
tion followed by the Slave Address Byte for a write or  
read operation. If the device is still busy with the  
internal write cycle, then no ACK will be returned. If the  
device has completed the internal write operation, an  
ACK will be returned and the host can then proceed  
with the read or write operation. Refer to figure 7 .  
Read operations are initiated in the same manner as  
write operations with the exception that the R/W bit of  
the Slave Address Byte is set to one. There are three  
basic read operations: Current Address Reads,  
Random Reads, and Sequential Reads.  
Current Address Read  
Internally, the device contains an address counter that  
maintains the address of the last word read or written  
incremented by one. After a read operation from the  
last address in the array, the counter will “roll over” to  
the first address in the array. After a write operation to  
the last address in a given page, the counter will “roll  
over” to the first address on the same page.  
Figure 7. Acknowledge Polling Sequence  
BYTE LOAD COMPLETED  
BY ISSUING STOP.  
ENTER ACK POLLING  
Upon receipt of the Slave Address Byte with the R/W  
bit set to one, the device issues an acknowledge and  
then transmits the eight bits of the Data Byte. The  
master terminates the read operation when it does not  
respond with an acknowledge during the ninth clock  
and then issues a stop condition. Refer to figure 8 for  
the address, acknowledge, and data transfer  
sequence.  
ISSUE  
START  
ISSUE SLAVE  
ADDRESS BYTE  
ISSUE STOP  
(READ OR WRITE)  
It should be noted that the ninth clock cycle of the read  
operation is not a “don’t care.” To terminate a read  
operation, the master must either issue a stop condi-  
tion during the ninth cycle or hold SDA HIGH during  
the ninth clock cycle and then issue a stop condition.  
ACK  
RETURNED?  
NO  
YES  
HIGH  
VOLTAGE  
CYCLE COMPLETE.  
CONTINUE  
Figure 8. Current Address Read Sequence  
NO  
S
SEQUENCE?  
SIGNALS  
FROM THE  
MASTER  
T
A
R
T
S
T
O
P
SLAVE  
ADDRESS  
YES  
SDA BUS  
S 1 0 1 0  
1
P
CONTINUE NORMAL  
READ OR WRITE  
COMMAND SEQUENCE  
A
C
K
ISSUE STOP  
SIGNALS  
FROM THE  
SLAVE  
DATA  
7027 FM 10  
PROCEED  
7027 FM 09  
7