X24012
Current Address Read
Random Read
Internally the X24012 contains an address counter that
maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either
areadorwrite)wastoaddressn,thenextreadoperation
would access data from address n + 1. Upon receipt of
the slave address with R/W set to one, the X24012
issues an acknowledge and transmits the eight bit word
during the next eight clock cycles. The read operation is
terminated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer to
Figure 7 for the sequence of address, acknowledge and
data transfer.
Randomreadoperationsallowthemastertoaccessany
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set to one, the master
must first perform a “dummy” write operation. The mas-
ter issues the start condition, and the slave address
followed by the word address it is to read. After the word
addressacknowledge,themasterimmediatelyreissues
thestartconditionandtheslaveaddresswiththeR/W bit
set to one. This will be followed by an acknowledge from
the X24012 and then by the eight bit word. The read
operationisterminatedbythemaster;bynotresponding
with an acknowledge and by issuing a stop condition.
RefertoFigure8fortheaddress, acknowledgeanddata
transfer sequence.
Figure 7. Current Address Read
S
T
S
T
O
P
SLAVE
ADDRESS
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
S
P
A
C
BUS ACTIVITY:
X24012
DATA
K
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Figure 8. Random Read
S
T
A
R
T
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS n
SLAVE
ADDRESS
BUS ACTIVITY:
MASTER
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24012
DATA n
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XICOR [ XICOR INC. ]
