X24001
Bus Timing
t
t
t
t
HIGH
LOW
R
F
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA IN
t
t
t
AA
DH
BUF
SDA OUT
3830 FHD F09
WRITE CYCLE LIMITS
Symbol
Parameter
Min.
Max.
Units
ms
(4)
t
Write Cycle Time
5
WR
3830 PGM T09
Write Cycle Timing
SCL
SDA
D0
t
WR
START
CONDTION
X24001
ADDRESS
3830 ILL F10.1
Note: (3) t
and t
are the delays required from the time V is stable until the specified operation can be initiated. These parameters
PUW CC
PUR
are periodically sampled and not 100% tested.
(4) The write cycle time is the time from the initiation of a write sequence to the end of the internal erase/program cycle. During the
write cycle, the X24001 bus interface circuits are disabled, SDA is high impedance, and the device does not respond to start
conditions.
8
XICOR [ XICOR INC. ]
