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X20C17SI-35 参数 Datasheet PDF下载

X20C17SI-35图片预览
型号: X20C17SI-35
PDF下载: 下载PDF文件 查看货源
内容描述: [Non-Volatile SRAM, 2KX8, 35ns, CMOS, PDSO28, PLASTIC, SOIC-28]
分类和应用: 静态存储器光电二极管内存集成电路
文件页数/大小: 12 页 / 178 K
品牌: XICOR [ XICOR INC. ]
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X20C17  
PIN CONFIGURATION  
Output Enable (OE)  
The Output Enable input controls the data output buff-  
ers and is used to initiate read and recall operations.  
Output Enable LOW disables a store operation regard-  
less of the state of CE, WE.  
Plastic  
A
A
A
A
A
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
V
A
A
7
6
5
4
3
CC  
8
2
Data In/Data Out (I/O –I/O )  
0
7
3
9
Data is written to or read from the X20C17 through the  
I/O pins. The I/O pins are placed in the high impedance  
state when either CE or OE is HIGH.  
WE  
OE  
4
5
A
A
A
6
A
2
1
0
10  
X20C17  
7
CE  
Write Enable (WE)  
8
I/O  
I/O  
I/O  
5
4
3
The Write Enable input controls the writing of data to  
the static RAM.  
9
I/O  
I/O  
I/O  
0
1
10  
11  
12  
PIN NAMES  
I/O2  
2
V
SS  
I/O  
1
Symbol  
A –A  
Description  
Address Inputs  
0
10  
SOIC  
I/O –I/O  
0
Data Input/Output  
Write Enable  
Chip Enable  
Output Enable  
+5V  
7
WE  
CE  
OE  
NC  
OE  
A
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
10  
CE  
I/O  
WE  
3
7
A
9
I/O  
I/O  
I/O  
I/O  
4
V
6
5
4
CC  
NC  
5
V
Ground  
SS  
A
8
6
X20C17  
V
7
CC  
DEVICE OPERATION  
3
8
V
SS  
NC  
The CE, OE, and WE inputs control the X20C17 opera-  
tion. The X20C17 byte-wide NOVRAM uses a 2-line  
control architecture to eliminate bus contention in a  
system environment. The I/O bus will be in a high  
impedance state when either OE or CE is HIGH.  
9
I/O  
2
A
7
A
6
10  
11  
12  
13  
14  
I/O1  
A
5
I/O  
0
NC  
A
0
A
4
A
1
RAM Operations  
A
3
A
2
RAM read and write operations are performed as they  
would be with any static RAM. A read operation  
requires CE and OE to be LOW. A write operation  
requires CE and WE to be LOW. There is no limit to the  
number of read or write operations performed to the  
RAM portion of the X20C17.  
PIN DESCRIPTIONS  
Addresses (A –A )  
0
10  
The Address inputs select an 8-bit memory location  
during a read or write operation.  
Memory Transfer Operations  
There are two memory transfer operations: a recall  
operation whereby the data stored in the E2PROM  
array is transferred to the RAM array; and a store oper-  
ation which causes the entire contents of the RAM  
array to be stored in the E2PROM array.  
Chip Enable (CE)  
The Chip Enable input must be LOW to enable all read/  
write operations. When CE is HIGH, power consump-  
tion is reduced.  
Characteristics subject to change without notice. 2 of 12