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X20C04JI-15T4 参数 Datasheet PDF下载

X20C04JI-15T4图片预览
型号: X20C04JI-15T4
PDF下载: 下载PDF文件 查看货源
内容描述: [Non-Volatile SRAM, 512X8, 150ns, CMOS, PQCC32, PLASTIC, LCC-32]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 15 页 / 62 K
品牌: XICOR [ XICOR INC. ]
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X20C04  
DEVICE OPERATION  
Power-Up Recall  
Upon power-up (VCC), the X20C04 performs an auto-  
matic array recall. When VCC minimum is reached, the  
recall is initiated, regardless of the state of CE, OE, WE  
and NE.  
The CE, OE, WE and NE inputs control the X20C04  
operation. The X20C04 byte-wide NOVRAM uses a  
2-line control architecture to eliminate bus contention in  
a system environment. The I/O bus will be in a high  
impedance state when either OE or CE is HIGH, or  
when NE is LOW.  
Write Protection  
The X20C04 has five write protect features that are  
employed to protect the contents of both the nonvolatile  
memory and the RAM.  
RAM Operations  
RAM read and write operations are performed as they  
would be with any static RAM. A read operation requires  
CE and OE to be LOW with WE and NE HIGH. A write  
operation requires CE and WE to be LOW with NE  
HIGH. There is no limit to the number of read or write  
operationsperformedtotheRAMportionoftheX20C04.  
• VCC Sense—All functions are inhibited when VCC is  
3.5V.  
• A RAM write is required before a Store Cycle is  
initiated.  
• Write Inhibit—Holding either OE LOW, WE HIGH,  
CE HIGH, or NE HIGH during power-up and power-  
down will prevent an inadvertent store operation.  
• Noise Protection—A combined WE, NE, OE and  
CE pulse of less than 20ns will not initiate a Store  
Cycle.  
• Noise Protection—A combined WE, NE, OE and  
CE pulse of less than 20ns will not initiate a recall  
cycle.  
Nonvolatile Operations  
WithNE LOW, recall operation is performed in the same  
manner as RAM read operation. A recall operation  
causes the entire contents of the E2PROM to be written  
into the RAM array. The time required for the operation  
to complete is 5µs or less. A store operation causes the  
entire contents of the RAM array to be stored in the  
nonvolatile E2PROM. The time for the operation to  
complete is 5ms or less.  
SYMBOL TABLE  
WAVEFORM  
INPUTS  
OUTPUTS  
Must be  
steady  
Will be  
steady  
May change  
from LOW  
to HIGH  
Will change  
from LOW  
to HIGH  
May change  
from HIGH  
to LOW  
Will change  
from HIGH  
to LOW  
Don’t Care:  
Changes  
Allowed  
Changing:  
State Not  
Known  
N/A  
Center Line  
is High  
Impedance  
3