Preliminary Information
X1288
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave
Address Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for t
.
WC
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; t
after a
WC
stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in
the Slave Address Byte.
(4) For reference only and not tested.
(5) V = V x 0.1, V = V x 0.9, f = 400KHz
IL
CC
IH
CC
SCL
(6) V = 0V
CC
(7) V
(8) V
(9) V
(10)V
= 0V
BACK
= V
=V , Others = GND or V
CC
SDA
SDA
SDA
SCL CC
=V
=V
, Others = GND or V
SCL BACK BACK
= GND or V , V
= GND or V , V
= GND or V
CC SCL
CC RESET CC
(11)I = 3.0mA at 5.5V, 1.5mA at 2.7V
OL
(12)
(13)Threshold voltages based on the higher of Vcc or Vback.
(14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15)Typical values are for T = 25°C
I
= -1.0mA at 5.5V, -0.4mA at 2.7V
OH
A
Capacitance T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Parameter
Output Capacitance (SDA, PHZ/IRQ, RESET)
Input Capacitance (SCL)
Max.
10
Units
pF
Test Conditions
= 0V
(1)
C
V
OUT
OUT
(1)
C
10
pF
V
= 0V
IN
IN
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
V
x 0.5
CC
Output Load
Standard Output Load
Figure 1. Standard Output Load for testing the device with V = 5.3V
CC
Equivalent AC Output Load Circuit for V
= 5V
CC
5.0V
5.0V
For V = 0.4V
OL
1316Ω
806Ω
1533Ω
and I = 3 mA
OL
PHZ/IRQ
SDA
100pF
100pF
6 of 31
REV 1.1.30 3/24/04
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