X1202
Figure 5. Set V
Level Sequence (V
= desired V
value)
TRIP
CC
TRIP
V
CC
V
= 15V
P
RESET
V
CC
0
1
2
3
4
5 6 7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4 5 6 7
SCL
SDA
AEh
00h
01h
00h
Resetting the V
Voltage
To reset the new V
voltage, apply more than 3V to
TRIP
TRIP
the V
pin and tie the RESET pin to the programming
CC
This procedure is used to set the V
voltage level. For example, if the current V
to a “native”
TRIP
voltage V . Then write 00h to address 03h. The stop bit of
P
is 4.4V
TRIP
a valid write operation initiates the V
sequence. Bring RESET to complete the operation.
programming
TRIP
and the new V
must be 4.0V, then the V
must
TRIP
TRIP
be reset. When V
is reset, the new V
is less
TRIP
TRIP
than 1.7V. This procedure must be used to set the volt-
age to a lower value.
Note: This operation also writes 00h to address 03h of
the EEPROM array.
Figure 6. Reset V
Level Sequence (V
> 3V)
TRIP
CC
V
= 15V
V
P
CC
RESET
V
CC
0
1 2 3 4 5 6 7
0
1
2 3
4
5 6
7
0
1
2 3
4
5 6
7
0 1 2 3 4 5 6 7
SCL
SDA
AEh
00h
03h
00h
Figure 7. Sample V
Reset Circuit
TRIP
V
P
4.7K
Adjust
Run
µC
RESET
1
8
7
6
5
X1202
(8-Pin SOIC)
2
3
4
V
TRIP
Adj.
SCL
SDA
Characteristics subject to change without notice. 8 of 23
REV 1.1.8 5/17/01
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