ISL29038
2
Each I C transaction ends with the master asserting a stop
condition (SDA rising while SCL remains high). For more
ISL29038 Configuration and
Control
I C Interface
2
™ 2
information about the I C standard, consult the Philips I C
specification documents.
2
2
2
Timing specifications are included in “I C Electrical
Specifications” on page 4. The timing parameters are defined in
Figure 4.
ISL29038 configuration and control is performed using the I C or
2
SMBus. The ISL29038’s I C interface slave address is internally
hard wired as 8’b1000100x, where x denotes the R/W bit.
2
2
The I C interface on the ISL29038 supports single and multiple
Every I C transaction begins with the master asserting a start
byte read and write transfers using the random-read/write
protocol. The ISL29038 does not support I C ‘Repeat Start’
protocol.
condition (SDA falling while SCL remains high). The first
transmitted byte is initiated by the master and includes 7
address bits and a R/W bit. The slave is responsible for pulling
SDA low during the ACK time after every transmitted byte.
2
Note that in most system implementations, the ISL29038 is
connected to a single I C master with one or more slave devices,
consequently, absence of ‘Repeat Start’ function does not
adversely affect I C bus system performance.
2
2
Figure 5 shows a sample one-byte read. The I C bus master
always drives the SCL (clock) line, while either the master or the
slave can drive the SDA (data) line.
2
START
DEVICE ADDRESS
A
A
A
9
REGISTER ADDRESS
DEVICE ADDRESS
A
A
DATA BYTE0
W
STOP START
2
I C DATA
2
I C SDA
A6 A5 A4 A3 A2 A1 A0 W
SDA DRIVEN BY MASTER
R7 R6 R5 R4 R3 R2 R1 R0
SDA DRIVEN BY MASTER
A
A
9
A6 A5 A4 A3 A2 A1 A0
W
SDA DRIVEN BY ISL29038
MASTER
2
I C SDA
SDA DRIVEN BY MASTER
A D7 D6 D5 D4 D3 D2 D1 D0
SLAVE (ISL29038)
2
I C CLK
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
2
FIGURE 5. I C DRIVER TIMING DIAGRAM FOR MASTER AND SLAVE CONNECTED TO COMMON BUS
FN7851.0
October 12, 2012
6
XICOR [ XICOR INC. ]
