TABLE I. Electrical performance characteristics - Continued.
│
│
│
│
│
│
│
│
│
│
│
│
│
Test
│Symbol
│
│
Conditions
-55°C ≤ TC ≤+125°C
VSS = 0 V,
│Group A
│subgroups │ types
│
│
│ Device
Limits
│ Unit
│
│
│
│
│
│
│
│
│
│
4.5 V ≤ VCC ≤ 5.5 V
│ Min
│ Max
│
│unless otherwise specified 1/
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Last byte loaded to
data polling
│tWHEL
│See figure 5 or 6
│ 9,10,11
│ All
│ 650 │ µs
│tEHEL 5/ │ as applicable
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
CE setup time
│tELWL 5/ │See figure 8
│ 9,10,11
│
│
│ 9,10,11
│
│
│ All
│
│
│ All
│
│
│ 5
│
│
│ 5
│
│
│
│
│
│
│
│
│ µs
│
│
│ µs
│
│
│
│
│
│
│
│
│
5/
Output set-up time
│tOVHWL
│
│
CE hold time
│tWHEH 5/ │
│ 9,10,11
│
│
│ All
│
│
│ 5
│
│
│
│
│
│ µs
│
│
│
│
│
5/
│
OE hold time
High voltage
Chip erase
│tWHOH
│
│
│VH 5/
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ 5
│
│
│
│
│ µs
│
│
│ V
│
│
│
│ 12
│
│
│ 13
│
│
│210 │ ms
│
│
│
5/
│tWLWH2
│
│
│
│
│
│
│
WE pulse width for │tWLWH15/ │
chip erase
│ 9,10,11
│
│ All
│
│ 10
│
│
│
│ ms
│
│
│
1/ DC and read mode.
2/ Connect all address inputs and OE to VIH and measure IOLZ and IOHZ with the output under test connected to VOUT
3/ All pins not being tested are to be open.
.
4/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the
limits specified in table I.
5/ Tested by application of specified timing signals and conditions, including:
Equivalent ac test conditions:
Devices: All.
Output load: 1 TTL gate and CL = 100 pF (minimum) or equivalent circuit.
Input rise and fall times ≤ 10 ns.
Input pulse levels: 0.4 V and 2.4 V.
Timing measurements reference levels:
Inputs: 1 V and 2 V.
Outputs: 0.8 V and 2 V.
6/ During a page write operation the cycle time defined by tWLWH and tWHWL2 shall not be less than 1 µs.
SIZE
STANDARD
5962-88525
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
D
8
DSCC FORM 2234
APR 97
XICOR [ XICOR INC. ]
