ISD1700 SERIES
5 PIN DESCRIPTION
Refer to Design Guide for details before performing any design or PCB layout.
PIN NAME
VCCD
FUNCTIONS
Digital Power Supply: Power supply for digital circuitry.
LED: An LED output.
LED
RESET: When active, the device enters into a known state.
RESET
MISO
Master In Slave Out: Data is shifted out on the falling edge of SCLK.
When the SPI is inactive ( SS = high), it’s tri-state.
MOSI
SCLK
Master Out Slave In: Data input of the SPI interface when ISD1700 is a
slave. Data is latched into the device on the rising edge of SCLK.
Serial Clock: Clock of the SPI interface.
Slave Select: Selects as a slave device and enables the SPI interface.
SS
VSSA
Analog Ground: Ground path for analog circuitry.
AnaIn
MIC+
MIC-
AnaIn: Auxiliary analog input to the device for recording or feed-through.
MIC+: Non-inverting input of the differential microphone signal.
MIC-: Inverting input of the differential microphone signal.
VSSP2
SP-
Ground: Ground path for negative PWM speaker drive.
SP-: The negative Class D PWM speaker output.
VCCP
Power Supply for PWM Speaker Driver: Power for PWM speaker drive.
SP+: The positive Class D PWM speaker output.
SP+
VSSP1
AUD/AUX
Ground: Ground path for positive PWM speaker drive.
Auxiliary Output: Either an AUD (current) or AUX (voltage) output.
Automatic Gain Control (AGC): The AGC adjusts the gain of the
microphone preamplifier circuitry.
AGC
Volume: This control has 8 levels of volume adjustment.
VOL
ROSC
Oscillator Resistor: A resistor determines the sample frequency of the
device, which sets the duration.
VCCA
Analog Power Supply. Power supply for analog circuitry.
Feed-through: Enable the feed-through path for AnaIn signal to the
outputs.
FT
Playback: Plays the recorded message individually, or plays messages
sequential in a looping mode.
PLAY
Record: When active, starts recording message.
REC
Erase: When active, can erase individual message or do global erase.
Forward: Advances to the next message from the current location.
An open drain output. Can review ready or interrupt status.
ERASE
FWD
RDY INT
VSSD
Digital Ground: Ground path for digital circuitry
Publication Release Date: January 23, 2007
- 7 -
Revision 1.3-S2
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